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    Implementing end-to-end credit management for enhanced large packet reassembly
    4.
    发明授权
    Implementing end-to-end credit management for enhanced large packet reassembly 失效
    实施端到端信用管理，增强大包重组

    公开(公告)号：US08675683B2

    公开(公告)日：2014-03-18

    申请号：US12764175

    申请日：2010-04-21

    申请人： Kenneth M. Valk ,  Bruce M. Walk

    发明人： Kenneth M. Valk ,  Bruce M. Walk

    IPC分类号： H04J3/24

    CPC分类号： H04L47/39 ,  H04L47/365

    摘要： A method and circuit for implementing end-to-end credit management for enhanced large packet reassembly in an interconnect system, and a design structure on which the subject circuit resides are provided. A transport layer provides buffering and credit control for a super packet received from a source device. A source transport layer sends an End-to-End (ETE) credit request message to a destination transport layer for an outstanding super packet transmission to a destination device. The destination transport layer grants credit to allow at least one source to send a super packet to the destination. The source transport layer fragments the super packet into multiple packets and sends all packets of the super packet only responsive to the credit request being granted by the destination transport layer that is needed to send all packets of the super packet.

    摘要翻译： 一种用于实现端到端信用管理以在互连系统中增强大分组重组的方法和电路，以及提供了主题电路所在的设计结构。 传输层为从源设备接收的超级分组提供缓冲和信用控制。 源传输层向目的地传输层发送端到端（ETE）信用请求消息，以发送到目的设备的未完成的超级分组传输。 目的地传输层授予信用以允许至少一个源向目的地发送超级分组。 源传输层将超级分组分解成多个分组，并且只响应发送所有超级分组的所有分组所需的目的传输层授予的信用请求，发送超分组的所有分组。

    Deadlock resolution in end-to-end credit protocol
    5.
    发明授权
    Deadlock resolution in end-to-end credit protocol 失效
    端到端信用协议中的死锁解决方案

    公开(公告)号：US08667205B2

    公开(公告)日：2014-03-04

    申请号：US13459548

    申请日：2012-04-30

    申请人： Nikolaos I. Chrysos ,  Fredy D. Neeser ,  Kenneth M. Valk

    发明人： Nikolaos I. Chrysos ,  Fredy D. Neeser ,  Kenneth M. Valk

    IPC分类号： G06F13/36

    CPC分类号： H04L47/39

    摘要： A system for deadlock resolution in end-to-end credit protocol includes a plurality of source controllers configured to receive data frames on an incoming link, wherein each source controller includes a plurality of credit counters. The system also includes a plurality of end controllers configured to receive data frames from the plurality of source controllers, wherein each end controller includes a buffer credit counter, a plurality of request counters, and an output buffer. Each of the plurality of credit counters corresponds to one of the plurality of end controllers and stores a number of credits received from that end controller. The buffer credit counter of each end controller stores a number of available credits of the end controllers. Each of the request counters corresponds to one of the plurality of source controllers and stores a number of credit requests received from that source controller.

    摘要翻译： 用于端对端信用协议中的死锁解析的系统包括多个源控制器，被配置为在传入链路上接收数据帧，其中每个源控制器包括多个信用计数器。 该系统还包括配置成从多个源控制器接收数据帧的多个终端控制器，其中每个终端控制器包括缓冲器信用计数器，多个请求计数器和输出缓冲器。 多个信用计数器中的每一个对应于多个终端控制器中的一个，并存储从该终端控制器接收到的信用数量。 每个终端控制器的缓冲区信用计数器存储终端控制器的许多可用信用。 每个请求计数器对应于多个源控制器中的一个，并且存储从该源控制器接收的许多信用请求。

    Techniques for Handling Commands in an Ordered Command Stream
    7.
    发明申请
    Techniques for Handling Commands in an Ordered Command Stream 审中-公开
    在有序的命令流中处理命令的技术

    公开(公告)号：US20090094385A1

    公开(公告)日：2009-04-09

    申请号：US11868603

    申请日：2007-10-08

    申请人： Ronald E. Freking ,  Ryan S. Haraden ,  David A. Shedivy ,  Kenneth M. Valk

    发明人： Ronald E. Freking ,  Ryan S. Haraden ,  David A. Shedivy ,  Kenneth M. Valk

    IPC分类号： G06F13/16

    CPC分类号： G06F9/3855 ,  G06F9/3857

    摘要： A technique for handling commands includes assigning respective first tags to ordered commands included in an ordered command stream. Respective second tags are then assigned to subsequent commands that follow an initial command (included in the ordered commands). Each of the respective second tags correspond to one the respective first tags that is associated with an immediate previous one of the ordered commands. The initial command is sent to an execution engine in a first cycle. At least one of the subsequent commands is sent to the execution engine prior to completion of execution of the initial command.

    摘要翻译： 用于处理命令的技术包括将相应的第一标签分配给包括在有序命令流中的有序命令。 然后将相应的第二个标签分配给遵循初始命令（包括在有序命令中）的后续命令。 每个相应的第二标签对应于与紧接着的先前的一个有序命令相关联的相应的第一标签中的一个。 初始命令在第一个周期内发送到执行引擎。 在完成初始命令的执行之前，至少一个随后的命令被发送到执行引擎。

    Method, Apparatus, and System Supporting Improved DMA Writes
    8.
    发明申请
    Method, Apparatus, and System Supporting Improved DMA Writes 审中-公开
    方法，设备和系统支持改进的DMA写入

    公开(公告)号：US20080301376A1

    公开(公告)日：2008-12-04

    申请号：US11756039

    申请日：2007-05-31

    申请人： Brian D. Allison ,  David A. Shedivy ,  Kenneth M. Valk ,  Brian T. Vanderpool

    发明人： Brian D. Allison ,  David A. Shedivy ,  Kenneth M. Valk ,  Brian T. Vanderpool

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0817

    摘要： A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation.

    摘要翻译： 存储器控制器接收DMA写操作流并将其排入队列中，执行先进先出（FIFO）顺序。 在处理特定DMA写入操作之前，存储器控制器获取目标存储器块的一致性所有权并将结果存储在低延迟数组中。 响应于获取一致性所有权，该低延迟阵列被更新为表示存储器控制器的一致性所有权的一致性状态。 在流水线阵列访问中，访问低延迟阵列和第二阵列，并且如果较低等待时间的第二阵列指示没有冲突指示的特定一致性状态，则存储器控制器指示可以执行特定的DMA写操作，其中 信号发生在从阵列访问管道的正常端的较高等待时间第一阵列获得的结果之前。 响应于信令，存储器控制器对由特定DMA写操作指示的存储器子系统进行更新。

    Hierarchical occupancy-based congestion management
    9.
    发明授权
    Hierarchical occupancy-based congestion management 有权
    基于层次占用的拥塞管理

    公开(公告)号：US09112784B2

    公开(公告)日：2015-08-18

    申请号：US13608120

    申请日：2012-09-10

    申请人： Yiyu L. Chen ,  Nikolaos I. Chrysos ,  Rolf Clauberg ,  Mircea R. Gusat ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

    发明人： Yiyu L. Chen ,  Nikolaos I. Chrysos ,  Rolf Clauberg ,  Mircea R. Gusat ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

    IPC分类号： G06F11/00 ,  H04L12/801 ,  H04L12/835

    CPC分类号： H04L47/10 ,  H04L47/30

    摘要： A system for hierarchical occupancy based congestion management includes a buffer embodied in a computer readable storage medium including a plurality of buffer units for storing packets of a data flow received from sources. The system includes a buffer manager that stores information about the packets stored in the buffer, including a selection criterion associated with each of the plurality of sources and a congestion estimator that monitors a congestion level in the buffer. The system also includes a occupancy sampler that randomly selects at least two occupied buffer units from the plurality of buffer units and identifies the source of the packet stored in each of the occupied buffer units and a congestion notification message generator that generates a congestion notification message; wherein if the congestion level in the buffer exceeds a threshold value the congestion notification message is sent to the identified source with a higher selection criteria.

    摘要翻译： 一种用于基于层次占用的拥塞管理系统，包括一个体现在计算机可读存储介质中的缓冲器，包括多个缓冲单元，用于存储从源接收的数据流的分组。 该系统包括缓冲器管理器，其存储关于存储在缓冲器中的分组的信息，包括与多个源中的每一个相关联的选择标准，以及监视缓冲器中的拥塞级别的拥塞估计器。 该系统还包括占用采样器，其从多个缓冲器单元中随机选择至少两个占用的缓冲器单元，并且识别存储在每个占用的缓冲器单元中的分组的源和产生拥塞通知消息的拥塞通知消息生成器; 其中如果所述缓冲器中的拥塞级别超过阈值，则所述拥塞通知消息以较高的选择标准被发送到所述识别的源。

    Deadlock resolution in end-to-end credit protocol
    10.
    发明授权
    Deadlock resolution in end-to-end credit protocol 失效
    端到端信用协议中的死锁解决方案

    公开(公告)号：US08677046B2

    公开(公告)日：2014-03-18

    申请号：US13570377

    申请日：2012-08-09

    申请人： Nikolaos I. Chrysos ,  Fredy D. Neeser ,  Kenneth M. Valk

    发明人： Nikolaos I. Chrysos ,  Fredy D. Neeser ,  Kenneth M. Valk

    IPC分类号： G06F13/36

    CPC分类号： H04L47/39

    摘要： A method for deadlock resolution in end-to-end credit protocol includes receiving a data frame and determining a number of credits required to transmit the data frame. The method also includes requesting and receiving credits from an end controller and responsively incrementing a credit counter. The method further includes determining if a value of the credit counter is greater than the number of credits required to transmit the data frame. Based on determining that the value of the credit counter is at least the number of credits required, the method includes transmitting the data frame to the end controller and decreasing the value of the credit counter by the number of credits required to transmit the data frame. Based on determining that the value of the credit counter is less than the number of credits required, the method includes transmitting a credit shortage notification to the end controller.

    摘要翻译： 端到端信用协议中的死锁解析方法包括接收数据帧并确定发送数据帧所需的信用数量。 该方法还包括从终端控制器请求和接收信用并响应地递增信用计数器。 该方法还包括确定信用计数器的值是否大于发送数据帧所需的信用数量。 基于确定信用计数器的值至少为所需信用数量，该方法包括将数据帧发送到终端控制器，并且通过发送数据帧所需的信用数减少信用计数器的值。 基于确定信用计数器的值小于所需信用数量，该方法包括向终端控制器发送信用不足通知。