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21.发明申请PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR HASH ALGORITHMS 有权用于执行哈希算法的指令支持的处理器和方法公开(公告)号：US20100250966A1
公开(公告)日：2010-09-30
申请号：US12415403
申请日：2009-03-31
CPC分类号： G06F12/1408 , G06F9/30007 , G06F9/3802 , G06F9/3836 , G06F9/3851 , G06F9/3895 , G06F21/76 , H04L9/0643 , H04L9/12 , H04L9/18 , H04L2209/125
摘要： A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include hash instructions defined within the ISA. In addition, the hash instructions may be executable by the cryptographic unit to implement a hash that is compliant with one or more respective hash algorithm specifications. In response to receiving a particular hash instruction defined within the ISA, the cryptographic unit may retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and generate a hash value of the set of input data blocks according to a hash algorithm that corresponds to the particular hash instruction.
摘要翻译： 包括用于实现散列算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发布执行编程器可选择的散列指令。 处理器可以包括可以接收执行指令的密码单元。 这些指令包括ISA内定义的散列指令。 此外，哈希指令可以由密码单元执行，以实现符合一个或多个相应散列算法规范的散列。 响应于接收在ISA内定义的特定散列指令，加密单元可以从处理器的预定的体系结构寄存器集中检索一组输入数据块，并且根据一个输入数据块生成一组输入数据块的哈希值 哈希算法对应于特定的哈希指令。
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22.发明授权Apparatus and method for reducing execution latency of floating point operations having special case operands 有权具有特殊情况操作数的浮点运算减少执行延迟的装置和方法公开(公告)号：US07437538B1
公开(公告)日：2008-10-14
申请号：US10881763
申请日：2004-06-30
IPC分类号： G06F9/40
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30123 , G06F9/3013 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3877 , G06F9/3891
摘要： An apparatus and method for floating-point special case handling. In one embodiment, a processor may include a first execution unit configured to execute a longer-latency floating-point instruction, and a second execution unit configured to execute a shorter-latency floating-point instruction. In response to the longer-latency floating-point instruction being issued to the first execution unit, the second execution unit may be further configured to detect whether a result of the longer-latency floating-point instruction is determinable from one or more operands of the longer-latency floating-point instruction independently of the first execution unit executing the longer-latency floating-point instruction. In response to detecting that the result is determinable, the second execution unit may be further configured to flush the longer-latency floating-point instruction from the first execution unit and to determine the result.
摘要翻译： 一种用于浮点特殊情况处理的装置和方法。 在一个实施例中，处理器可以包括被配置为执行较长延迟浮点指令的第一执行单元，以及被配置为执行较短延迟浮点指令的第二执行单元。 响应于向第一执行单元发出的较长延迟的浮点指令，第二执行单元还可以被配置为检测长延迟浮点指令的结果是否可以从所述第一执行单元的一个或多个操作数确定 更长延迟的浮点指令独立于执行较长延迟浮点指令的第一执行单元。 响应于检测到结果是可确定的，第二执行单元可以被进一步配置为从第一执行单元刷新长延迟浮点指令并确定结果。
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23.发明授权Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window 有权注册窗口管理使用第一个流水线更改当前窗口，第二个管道从旧窗口读取操作数，并将操作数写入新窗口公开(公告)号：US07216216B1
公开(公告)日：2007-05-08
申请号：US10881556
申请日：2004-06-30
CPC分类号： G06F9/30127 , G06F9/30043 , G06F9/3012 , G06F9/3867 , G06F9/3885
摘要： In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.
摘要翻译： 在一个实施例中，处理器被配置为执行窗口交换指令。 处理器包括寄存器文件（包括多个寄存器）以及耦合到寄存器文件的第一和第二执行单元。 与第一执行单元相关联的第一流水线具有第一数量的流水线级，并且与第二执行单元相关联的第二流水线具有第二数量的流水线级。 第一执行单元被配置为响应于指令将当前寄存器窗口从第一寄存器窗口改变到寄存器堆中的第二寄存器窗口。 第二执行单元被配置为执行由指令定义的操作，并将结果写入寄存器文件。 第二数量的流水线级超过第一个数字，从而在写入结果之前在寄存器文件中建立第二个寄存器窗口。
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24.发明授权Partitioned shifter for single instruction stream multiple data stream (SIMD) operations 有权用于单指令流分多个数据流（SIMD）操作的分区移位器公开(公告)号：US07099910B2
公开(公告)日：2006-08-29
申请号：US10408132
申请日：2003-04-07
IPC分类号： G06F7/485
CPC分类号： G06F7/485 , G06F5/012 , G06F2207/382 , G06F2207/3828
摘要： A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
摘要翻译： 一种在单个浮点执行单元内实现单指令流多数据流操作和双精度浮点运算的方法，该方法包括：提供具有双向对准器和双向归一化器的浮点单元， 要执行单个指令流多数据流操作还是执行双精度操作，并且基于是要执行单个指令流多数据流操作还是双精度操作来选择性地归一化值 被执行。
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25.发明授权Processor pipeline which implements fused and unfused multiply-add instructions 有权处理器管道，其实现融合和未加密的乘法加法指令公开(公告)号：US08977670B2
公开(公告)日：2015-03-10
申请号：US13469212
申请日：2012-05-11
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3884
摘要： Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.
摘要翻译： 在融合的乘法加法管道中实现未经加密的乘法加法指令。 系统可以包括具有用于接收加法项的输入的对准器，具有用于接收第一值的两个输入和用于乘法的第二值的乘法器树，以及第一进位保存加法器（CSA），其中第一CSA可以接收部分 乘数树中的乘积和对准器的对齐加法项。 该系统可以包括可以接收第一部分乘积，第二部分乘积和对齐的加法项的融合/未融合乘法（FUMA）块，其中第一部分乘积和第二部分乘积不被截断。 FUMA块可以使用第一部分乘积，第二部分积和对齐的相加项来执行未融合的加法运算或融合乘法运算，例如取决于操作码或模式位。
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公开(公告)号：US20130179664A1
公开(公告)日：2013-07-11
申请号：US13345391
申请日：2012-01-06
CPC分类号： G06F9/3895 , G06F7/49936 , G06F7/535 , G06F7/5375 , G06F9/3001 , G06F9/3875 , G06F9/3885
摘要： Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.
摘要翻译： 公开了涉及包括用于划分和/或平方根操作的硬件支持的集成电路的技术。 在一个实施例中，公开了一种集成电路，其包括分割单元，该分割单元又包括归一化电路和多个除法引擎。 归一化电路被配置为归一化一组操作数。 每个分频引擎被配置为对从归一化电路接收的相应的归一化操作数集进行操作。 在一些实施例中，集成电路包括调度器单元，其被配置为选择用于向包括该分割单元的多个执行单元发布的指令。 调度器单元还被配置为保持指示当前正在由分割单元操作的指令的数量的计数器，并且基于计数器确定是否计划用于发布到分割单元的后续指令。
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公开(公告)号：US08458446B2
公开(公告)日：2013-06-04
申请号：US12570682
申请日：2009-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30127 , G06F9/3013 , G06F9/30141 , G06F9/3851 , G11C8/16
摘要： A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.
摘要翻译： 处理器包括：指令获取单元，被配置为发出用于执行的指令，其中从多个线程中选择指令，其中每个给定指令具有对应的线程标识符，并且其中至少一些指令经由寄存器指定操作数 身份标识。 寄存器文件存储指令可用的操作数，并且可以包括几个存储体，每个存储体对应于寄存器标识符，并且包括与多个线程对应的多个条目，其中条目被配置为存储数据值。 响应于接收到针对给定线程标识符读取特定寄存器标识符的请求，寄存器文件可以被配置为对给定的线程标识符进行解码以从对应于给定线程标识符的存储体检索条目。 寄存器文件还可以从检索到的条目中选择与要输出的特定寄存器标识符对应的数据值。
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公开(公告)号：US20120087492A1
公开(公告)日：2012-04-12
申请号：US13291026
申请日：2011-11-07
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： Described is an execution unit for performing at least part of the Data Encryption Standard that includes a Left Half input; a Key input; and a Table input, as well as a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output that is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 描述了用于执行包括左半输入的数据加密标准的至少一部分的执行单元; 一键输入 和Table输入，以及被配置为接收Table输入的第一组晶体管，执行表查找和输出数据。 执行单元还包括具有两个输入的第一异或运算符和被配置为接收左半输入和键输入的输出。 执行单元还包括具有两个输入的第二异或运算符和被配置为接收由第一组晶体管输出的数据并且接收第一个异或运算符的输出的输出。 执行单元还包括具有两个输入的第三异或运算符和被配置为接收左半输入和由第一组晶体管输出的数据的输出。
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29.发明授权公开(公告)号：US08078942B2
公开(公告)日：2011-12-13
申请号：US11849749
申请日：2007-09-04
CPC分类号： G06F11/10
摘要： In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
摘要翻译： 在一个实施例中，处理器包括被配置为存储推测寄存器状态的第一寄存器文件，被配置为存储提交寄存器状态的第二寄存器文件，检查电路和控制单元。 第一个寄存器文件由第一个错误保护方案保护，第二个寄存器文件由第二个错误保护方案保护。 耦合检查电路以响应于处理器选择要提交的第一指令，接收从第一寄存器文件读取的值和对应的一个或多个校验位以提交给第二寄存器堆。 检查电路被配置为响应于该值和校验位来检测该值中的错误。 耦合到检查电路，控制单元被配置为响应于由检查电路检测到的错误而引起第一指令的再次执行。
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30.发明申请PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS THAT UTILIZE MULTIPLE REGISTER WINDOWS 有权处理器和方法提供指令支持使用多个寄存器窗口的指令公开(公告)号：US20110296142A1
公开(公告)日：2011-12-01
申请号：US12790074
申请日：2010-05-28
CPC分类号： G06F9/30127 , G06F7/5324 , G06F9/30032 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3867 , G06F21/556
摘要： A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.
摘要翻译： 包括对使用多个寄存器窗口的大操作数指令的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的指令。 处理器还可以包括指令执行单元，其在操作期间从指令获取单元接收执行指令，并执行在ISA内定义的大操作数指令，其中大操作数指令的执行取决于多个寄存器 布置在多个寄存器窗口内。 处理器还可以包括控制电路（其可以包括在提取单元，执行单元或处理器内的其他地方），其确定不存在大操作数指令所依赖的寄存器窗口中的一个或多个。 响应于确定这些寄存器窗口中的一个或多个不存在，控制电路使它们被恢复。
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