公开(公告)号：US20060028888A1

公开(公告)日：2006-02-09

申请号：US11188184

申请日：2005-07-20

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US20050248042A1

公开(公告)日：2005-11-10

申请号：US11121864

申请日：2005-05-04

申请人： Jong-Eon Lee ,  Chul-Soo Kim ,  Byung-Hoon Jeong ,  Jun-Hyung Kim ,  Young-Sun Min

发明人： Jong-Eon Lee ,  Chul-Soo Kim ,  Byung-Hoon Jeong ,  Jun-Hyung Kim ,  Young-Sun Min

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882

摘要： A semiconductor memory device having a memory cell array includes a plurality of first signal lines arranged on the memory cell array in the same direction and a plurality of second signal lines arranged on the memory cell array in a perpendicular direction to the first signal lines. The first signal lines are alternately arranged on at least two layers, and the second signal lines are arranged on a layer where the first signal lines are not arranged.

摘要翻译： 具有存储单元阵列的半导体存储器件包括沿着相同方向布置在存储单元阵列上的多个第一信号线和沿与第一信号线垂直的方向布置在存储单元阵列上的多个第二信号线。 第一信号线交替布置在至少两层上，并且第二信号线被布置在不布置第一信号线的层上。