公开(公告)号：US07855926B2

公开(公告)日：2010-12-21

申请号：US11188184

申请日：2005-07-20

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US20060028888A1

公开(公告)日：2006-02-09

申请号：US11188184

申请日：2005-07-20

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US20110069568A1

公开(公告)日：2011-03-24

申请号：US12952328

申请日：2010-11-23

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/08 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US07366822B2

公开(公告)日：2008-04-29

申请号：US10840268

申请日：2004-05-07

申请人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

发明人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

IPC分类号： G06F12/00 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C11/4082 ,  G11C11/4087

摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

摘要翻译： 半导体存储器件包括多个存储体。 数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。 半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。 半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少 。

公开(公告)号：US09336906B2

公开(公告)日：2016-05-10

申请号：US14503691

申请日：2014-10-01

申请人： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

发明人： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C11/406 ,  G11C17/16

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

摘要翻译： 半导体存储器件包括存储单元阵列，修复控制电路和刷新控制电路。 存储单元阵列包括多个存储单元和多个冗余存储单元。 修复控制电路在修复模式期间接收修复命令并对多个存储单元中的第一有缺陷存储单元执行修复操作。 半导体存储器件可以响应于修复命令在修复模式下操作。 刷新控制电路在修复模式期间对多个存储单元中的无缺陷存储单元执行刷新操作。

公开(公告)号：US08488399B2

公开(公告)日：2013-07-16

申请号：US13108130

申请日：2011-05-16

申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

IPC分类号： G11C7/00

CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

公开(公告)号：US20110286254A1

公开(公告)日：2011-11-24

申请号：US13108130

申请日：2011-05-16

申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

公开(公告)号：US07423896B2

公开(公告)日：2008-09-09

申请号：US11789395

申请日：2007-04-24

申请人： Sang-Bo Lee

发明人： Sang-Bo Lee

IPC分类号： G11C5/06

CPC分类号： G11C7/18 ,  G11C7/062

摘要： A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

摘要翻译： 存储器件包括一个解码器，它同时设置第一逻辑电平的操作控制信号和列选择线信号。 另外，本地读出放大器具有至少一个开关装置，该开关装置由处于第一逻辑电平的操作控制信号导通，以将至少一个本地I / O线耦合到至少一个全局I / O线。 此外，被设置为并联的信号线从解码器发送操作控制信号和列选择线信号。

公开(公告)号：US07219026B2

公开(公告)日：2007-05-15

申请号：US11031104

申请日：2005-01-07

申请人： Hyun-Jin Kim ,  Sang-Bo Lee

发明人： Hyun-Jin Kim ,  Sang-Bo Lee

IPC分类号： G06F19/00

CPC分类号： G11C7/22 ,  G11C7/16 ,  G11C7/222

摘要： A frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital (A/D) converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. Related methods and integrated circuit memory devices are also discussed.

摘要翻译： 频率测量电路可以包括边缘检测器，电荷泵和模数（A / D）转换器。 边缘检测器可以被配置为响应于输入时钟信号的边缘产生输出脉冲。 电荷泵可以被配置为响应于来自边缘检测器的输出脉冲而产生输出信号。 模拟数字（A / D）转换器可以被配置为将输出信号转换成表示输入时钟信号的频率的数字值。 还讨论了相关方法和集成电路存储器件。

公开(公告)号：US20050195672A1

公开(公告)日：2005-09-08

申请号：US11068353

申请日：2005-02-28

申请人： Sang-Bo Lee

发明人： Sang-Bo Lee

IPC分类号： G11C7/06 ,  G11C7/02 ,  G11C11/4091 ,  G11C11/419

CPC分类号： G11C11/4091 ,  G11C7/04

摘要： A current sense amplifier includes first and second P type MOS transistors having source nodes connected to first and second sensing inputs, respectively, and gate and drain nodes being cross-coupled to each other. First and second N type MOS transistors have drain nodes connected to first and second sensing outputs, respectively, the first and second sensing outputs corresponding to the drain nodes of the first and second P type MOS transistors, respectively, the first and second N type MOS transistors having respective gate nodes connected to a power supply voltage. Third and fourth N type MOS transistors have drain nodes connected to the first and second sensing outputs, respectively, and gate nodes connected to a bias voltage node so that respective current paths are established from the first and second sensing outputs to a common reference node.

摘要翻译： 电流检测放大器包括分别连接到第一和第二感测输入的源节点的第一和第二P型MOS晶体管，并且栅极和漏极节点彼此交叉耦合。 第一和第二N型MOS晶体管具有分别连接到第一和第二感测输出的漏极节点，分别对应于第一和第二P型MOS晶体管的漏极节点的第一和第二感测输出，第一和第二N型MOS 具有连接到电源电压的各个栅极节点的晶体管。 第三和第四N型MOS晶体管分别具有连接到第一和第二感测输出的漏极节点，以及连接到偏置电压节点的栅极节点，使得各自的电流路径从第一和第二感测输出建立到公共参考节点。