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21.发明授权Systems, apparatuses, and methods for performing a double blocked sum of absolute differences 有权用于执行绝对差异的双重阻塞和的系统，装置和方法公开(公告)号：US09582464B2
公开(公告)日：2017-02-28
申请号：US13992229
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
CPC分类号： G06F9/3001 , G06F7/50 , G06F7/544 , G06F9/30036 , G06F9/3836 , G06F9/3877 , G06F15/78 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。
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公开(公告)号：US20150088946A1
公开(公告)日：2015-03-26
申请号：US13977086
申请日：2011-12-28
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30036
摘要： A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一种方面的方法包括接收浮点缩放指令。 浮点缩放指令指示包括一个或多个浮点数据元素的第一源，包括一个或多个对应浮点数据元素的第二源和目的地。 响应于浮点缩放指令，结果存储在目的地中。 结果包括一个或多个相应的结果浮点数据元素，每个元素包括第二源的相应浮点数据元素乘以第一源的一个或多个浮点数据元素的基数，并将其表示为 第一个源的相应浮点数据元素。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US10095516B2
公开(公告)日：2018-10-09
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
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公开(公告)号：US09678751B2
公开(公告)日：2017-06-13
申请号：US13977612
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
发明人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30101
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
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25.发明授权Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction 有权用于响应于单个指令执行蝶形水平和交叉加法或减法的系统，装置和方法公开(公告)号：US09459865B2
公开(公告)日：2016-10-04
申请号：US13992236
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F17/142
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行向量包装蝶形水平交叉加法或减法的系统，装置和方法响应于包括目的地向量寄存器操作数的单向量包装蝶式水平交叉加减法指令，源 描述向量寄存器操作数，立即数和操作码。
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26.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL ADD OR SUBTRACT IN RESPONSE TO A SINGLE INSTRUCTION 有权用于执行水平添加或分类的系统，设备和方法对单一指令的响应公开(公告)号：US20140013075A1
公开(公告)日：2014-01-09
申请号：US13992230
申请日：2011-12-23
申请人： Mostafa Hagog , Elmoustapha Ould-Aumed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Mostafa Hagog , Elmoustapha Ould-Aumed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数，源向量寄存器操作数，单向量封装的水平加法或减法指令，对打包数据元素进行水平加或减， 并描述操作码。
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27.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A DOUBLE BLOCKED SUM OF ABSOLUTE DIFFERENCES 有权用于执行双重阻塞的绝对差异的系统，装置和方法公开(公告)号：US20140019713A1
公开(公告)日：2014-01-16
申请号：US13992229
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F15/78
CPC分类号： G06F9/3001 , G06F7/50 , G06F7/544 , G06F9/30036 , G06F9/3836 , G06F9/3877 , G06F15/78 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。
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公开(公告)号：US20140006755A1
公开(公告)日：2014-01-02
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F7/52 , G06F9/30018 , G06F9/30036
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
摘要翻译： 描述了具有指令执行流水线的装置，其具有支持向量乘法加法指令的向量功能单元。 向量乘以相乘指令乘以两个向量的各个K位元素，并将其各自产物的一部分与X位累加器中的另一个相应输入操作数进行累加，其中X大于K.
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公开(公告)号：US09619226B2
公开(公告)日：2017-04-11
申请号：US13992230
申请日：2011-12-23
申请人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
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公开(公告)号：US09448765B2
公开(公告)日：2016-09-20
申请号：US13977086
申请日：2011-12-28
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30036
摘要： A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一个方面的方法包括接收浮点缩放指令。 浮点缩放指令指示包括一个或多个浮点数据元素的第一源，包括一个或多个对应浮点数据元素的第二源和目的地。 响应于浮点缩放指令，结果存储在目的地中。 结果包括一个或多个相应的结果浮点数据元素，每个元素包括第二源的相应浮点数据元素乘以第一源的一个或多个浮点数据元素的基数，并将其代入 第一个源的相应浮点数据元素。 公开了其它方法，装置，系统和指令。
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