公开(公告)号：US06760307B2

公开(公告)日：2004-07-06

申请号：US09141134

申请日：1998-08-27

申请人： David S. Dunning ,  Richard S. Jensen

发明人： David S. Dunning ,  Richard S. Jensen

IPC分类号： H04L1228

CPC分类号： H04L1/0057 ,  H04L1/08 ,  H04L1/1635 ,  H04L1/1806 ,  H04L1/1835 ,  H04L1/1877 ,  H04L1/188 ,  H04L1/1883 ,  H04L41/06 ,  H04L47/10 ,  H04L47/17 ,  H04L47/26 ,  H04L2001/0096 ,  H04L2001/0097

摘要： Link-based flow control requires each link transmitter to retain packets until such time as they are acknowledged by the link receiver. Depending on the type of acknowledge, the transmitter will then either retry or de-allocate the packets. To improve throughput, the present invention includes an optimistic transmitter, which transmits packets without knowing the state of the receiver buffer. By so doing, the present invention improves the latency caused by delays in transit time between nodes. Furthermore, single acknowledgments are used to indicate successful receipt of multiple packets. Single negative acknowledgments are used to indicate successful receipt of all data between a last acknowledged data packet and a packet associated with the negative acknowledgment, which was received with errors.

摘要翻译： 基于链路的流量控制要求每个链路发送器保留分组，直到它们被链路接收机确认为止。 根据应答的类型，发射机将会重试或取消分配数据包。 为了提高吞吐量，本发明包括一种乐观的发送器，其在不知道接收器缓冲器的状态的情况下发送分组。 通过这样做，本发明改善了由节点之间的传送时间延迟引起的等待时间。 此外，单个确认用于指示成功接收多个分组。 单个否定确认用于指示在最后确认的数据分组和与否定确认相关联的分组之间的所有数据的成功接收，该分组被错误地接收。

公开(公告)号：US06683850B1

公开(公告)日：2004-01-27

申请号：US09141151

申请日：1998-08-27

申请人： David S. Dunning ,  Ken Drottar

发明人： David S. Dunning ,  Ken Drottar

IPC分类号： H04L108

CPC分类号： H04L1/0057 ,  H04L1/0061 ,  H04L1/0072 ,  H04L1/08 ,  H04L1/16 ,  H04L1/1635 ,  H04L1/1806 ,  H04L1/1835 ,  H04L1/1877 ,  H04L1/188 ,  H04L1/1883 ,  H04L41/0654 ,  H04L69/22 ,  H04L2001/0096

摘要： Link-based flow control requires each link transmitter to retain packets until such time as they are acknowledged by the link receiver. Depending on the type of acknowledge, the transmitter will then either retry or de-allocate the packets. The NG I/O flow control of the present invention is credit based. At power up, each end of a link determines buffer size, deferring to the smaller implemented buffer if size is different. A transmitter will not send a packet unless buffer space at the receiver is available. Transmitter and receiver also synchronize on width of the link ID counter. Each link transmitter assigns an ordered ID (beginning with zero) to each sent packet. The link receiver tests the checksum of each delivered packet. If the packet tests with no error, the receiver sends a positive acknowledge (ACK) back to the transmitter. Flow control is either contained in its own packet or is appended to a packet assembling for transmission back. Some period of time can be consumed while the receiver attempts to acknowledge the transmitter. In the interests of efficiency, a receiver can ACK out-of-order to de-allocate buffer space for the named transaction and any other sequentially previous transactions outstanding at the transmitter. In exchange for this performance benefits, the receiver assumes responsibility for tracking transmit ID sequence. This audition activity reduces the opportunity for undetected packets. In the case of negative acknowledge (NAK), the transmitter may still de-allocate for sequentially previous transactions. NAK instructs the transmitter to resend the indicated packet and any packets that have been sent since then. Each transmitter has a configurable interval timer for the link acknowledge cycle. Each transmitter has a configurable iteration counter for NAK. Rather than congest the link, a transmitter that has run through either counter is obliged to return the undeliverable packet to its source.

公开(公告)号：US07747888B2

公开(公告)日：2010-06-29

申请号：US11978849

申请日：2007-10-30

申请人： Tim Frodsham ,  Michael J. Tripp ,  David J. O'Brien ,  Muraleedhara Navada ,  Naveen Cherukuri ,  Sanjay Dabral ,  David S. Dunning ,  Theodore Z. Schoenborn

发明人： Tim Frodsham ,  Michael J. Tripp ,  David J. O'Brien ,  Muraleedhara Navada ,  Naveen Cherukuri ,  Sanjay Dabral ,  David S. Dunning ,  Theodore Z. Schoenborn

IPC分类号： G06F1/12 ,  G06F1/14

CPC分类号： G06F13/4273 ,  G06F5/06

摘要： A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

摘要翻译： 一种促进点对点（PtP）网络中总线代理之间确定性的技术。 更具体地，本发明的实施例涉及补偿公共系统接口（CSI）总线代理的PtP网络内的链路延迟，数据偏移和时钟偏移的技术。

公开(公告)号：US07711878B2

公开(公告)日：2010-05-04

申请号：US10851369

申请日：2004-05-21

申请人： Naveen Cherukuri ,  Sanjay Dabral ,  David S. Dunning ,  Tim Frodsham ,  Theodore Z. Schoenborn

发明人： Naveen Cherukuri ,  Sanjay Dabral ,  David S. Dunning ,  Tim Frodsham ,  Theodore Z. Schoenborn

IPC分类号： G06F13/42 ,  G08C25/02 ,  H04L1/18 ,  G06F15/16

CPC分类号： G06F13/4273

摘要： A method and apparatus for advancing initialization messages when initializing an interface is presented. In one embodiment, one of a sequence of training sequence messages are sent in serial mode across the data lanes of a generally-parallel interface between two agents. When one agent correctly receives a fixed number of messages, it may begin sending its messages with an acknowledgement. Thereafter, when that agent correctly receives a fixed number of messages including an acknowledgement, that agent may advance to sending the next training sequence messages in the sequence.

摘要翻译： 提出了一种在初始化界面时推进初始化消息的方法和装置。 在一个实施例中，训练序列消息序列中的一个在两个代理之间的通常并行接口的数据通道上以串行模式发送。 当一个代理正确接收到固定数量的消息时，它可以开始发送其确认消息。 此后，当该代理正确地接收到包括确认的固定数量的消息时，该代理可以推进以顺序发送下一个训练序列消息。

公开(公告)号：US07203853B2

公开(公告)日：2007-04-10

申请号：US10302295

申请日：2002-11-22

申请人： Andrew W. Martwick ,  Ken Drottar ,  David S. Dunning ,  Zale T. Schoenborn ,  Andrew M. Volk ,  Ronald W. Swartz ,  Dennis J. Miller

发明人： Andrew W. Martwick ,  Ken Drottar ,  David S. Dunning ,  Zale T. Schoenborn ,  Andrew M. Volk ,  Ronald W. Swartz ,  Dennis J. Miller

IPC分类号： G06F12/00

CPC分类号： G06F1/3209 ,  G06F1/325 ,  G06F1/3253 ,  Y02D10/151

摘要： An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

摘要翻译： 描述了串行数据链路上的低延迟功率管理的装置和方法。 在一个实施例中，该方法包括在电气空闲状态期间在接收机操作期间检测电空闲出口状况。 一旦检测到，则根据一个或多个接收到的数据同步训练模式执行数据同步。 最后，当在确定的同步重建周期内执行同步时，接收机将根据正常功率状态恢复操作。 因此，所描述的实施例示出了3GIO链路内的电源管理的开环低延迟功率恢复操作。

公开(公告)号：US06781434B2

公开(公告)日：2004-08-24

申请号：US10247752

申请日：2002-09-19

申请人： Richard S. Jensen ,  David S. Dunning ,  Michael M. DeSmith

发明人： Richard S. Jensen ,  David S. Dunning ,  Michael M. DeSmith

IPC分类号： H03K1730

CPC分类号： G11C27/024 ,  G11C27/026 ,  H03K17/162

摘要： A switch circuit having low charge dumping characteristics includes multiple parallel connected switching transistors and one or more associated cancellation transistors. The switching transistors perform basic switching functions within the switch circuit in response to a digital signal. During transitions of the digital signal, the switching transistors dump charge on an output node thereof due to parasitic capacitances within the devices. The cancellation transistor(s) dumps charge of an opposite polarity on the output node to cancel the charge dumped by the switching transistors. Two switching transistors are used for each cancellation transistor so that equal sized devices can be used throughout the switch circuit.

摘要翻译： 具有低电荷倾倒特性的开关电路包括多个并联的开关晶体管和一个或多个相关联的消除晶体管。 开关晶体管响应于数字信号在开关电路内执行基本的开关功能。 在数字信号的转换期间，开关晶体管由于器件内的寄生电容而在其输出节点上转储电荷。 消除晶体管在输出节点处转移相反极性的电荷，以消除由开关晶体管倾倒的电荷。 两个开关晶体管用于每个消除晶体管，使得在整个开关电路中可以使用等大小的器件。

公开(公告)号：US06687840B1

公开(公告)日：2004-02-03

申请号：US09557099

申请日：2000-04-21

申请人： Ken Drottar ,  David S. Dunning

发明人： Ken Drottar ,  David S. Dunning

IPC分类号： G06F1342

CPC分类号： H04L47/10 ,  H04L69/14 ,  H04L69/324 ,  Y02D50/30

摘要： A method, apparatus, and system are provided for multi-link extensions and bundle skew management. According to one embodiment, multiple parallel links between two or more devices are combined into a single channel, and cells on the various links are received in a round-robin order, and variations in flight time between the various links are compensated through a timer at each receive port of the bundle.

摘要翻译： 提供了一种方法，装置和系统用于多链路扩展和捆绑偏移管理。 根据一个实施例，两个或多个设备之间的多个并行链路被组合成单个信道，并且以循环次序接收各个链路上的小区，并且通过定时器在各个链路之间的飞行时间的变化被补偿 每个接收端口的捆绑。

公开(公告)号：US6094683A

公开(公告)日：2000-07-25

申请号：US137168

申请日：1998-08-20

申请人： Ken Drottar ,  David S. Dunning

发明人： Ken Drottar ,  David S. Dunning

IPC分类号： H04L1/00 ,  H04L1/16 ,  H04L12/24 ,  H04L29/06 ,  H04L29/08 ,  G06F15/173 ,  G06F15/16

CPC分类号： H04L69/22 ,  H04L69/14 ,  H04L1/16 ,  H04L2001/0092 ,  H04L2001/0096 ,  H04L41/0654 ,  H04L69/324 ,  Y02B60/33

摘要： A technique for bundling links is provided for increasing bandwidth and reducing latency. Two nodes in a network are configured to bundle two or more links connected between the two nodes. Data is transmitted between the two nodes by striping data over each link of the bundle. Data is transmitted in cells, and one or more cells are transmitted over each link of the bundle. The cells transmitted on one or more of the links include routing information.

摘要翻译： 提供捆绑链接的技术用于增加带宽并减少延迟。 网络中的两个节点被配置为捆绑连接在两个节点之间的两个或多个链路。 通过在捆绑的每个链路上分条数据，在两个节点之间传输数据。 数据在单元中传输，并且一个或多个单元通过该组的每个链路传输。 在一个或多个链路上发送的小区包括路由信息。

公开(公告)号：US20150006849A1

公开(公告)日：2015-01-01

申请号：US13930976

申请日：2013-06-28

申请人： Jianping Xu ,  Asit K. Mishra ,  Joshua B. Fryman ,  David S. Dunning

发明人： Jianping Xu ,  Asit K. Mishra ,  Joshua B. Fryman ,  David S. Dunning

IPC分类号： G06F15/80

CPC分类号： G06F15/17325

摘要： A reconfigurable tree apparatus with a bypass mode and a method of using the reconfigurable tree apparatus are disclosed. The reconfigurable tree apparatus uses a short-circuit register to selectively designate participating agents for such operations as barriers, multicast, and reductions. The reconfigurable tree apparatus enables an agent to initiate a barrier, multicast, or reduction operation, leaving software to determine the participating agents for each operation. Although the reconfigurable tree apparatus is implemented using a small number of wires, multiple in-flight barrier, multicast, and reduction operations can take place. The method and apparatus have low complexity, easy reconfigurability, and provide the energy savings necessary for future exa-scale machines.

摘要翻译： 公开了具有旁路模式的可重构树装置和使用可重构树装置的方法。 可重构树装置使用短路寄存器来选择性地指定用于诸如屏障，多播和减少的操作的参与代理。 可重构树装置使得代理能够启动屏障，多播或缩减操作，使软件确定每个操作的参与代理。 虽然使用少量的线路来实现可重构树设备，但是可以进行多个飞行中的屏障，多播和减少操作。 该方法和装置具有复杂性低，易于重新配置，并为未来的规模化机器提供所需的能量节省。

公开(公告)号：US07936684B2

公开(公告)日：2011-05-03

申请号：US11842280

申请日：2007-08-21

申请人： Theodore Z. Schoenborn ,  Andrew W. Martwick ,  David S. Dunning

发明人： Theodore Z. Schoenborn ,  Andrew W. Martwick ,  David S. Dunning

IPC分类号： H04J1/16

CPC分类号： G06F11/27 ,  G01R31/31716 ,  H04L43/50

摘要： In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，芯片包括控制电路，以提供带内信号，带内输出端口和发射器，以将带内信号传输到带内输出端口。 控制电路选择性地包括带内信号中的回送启动命令。 描述和要求保护其他实施例。