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公开(公告)号：US20110037493A1
公开(公告)日：2011-02-17
申请号：US12539732
申请日：2009-08-12
申请人： William J. Cote , Yi Feng , Oliver D. Patterson
发明人： William J. Cote , Yi Feng , Oliver D. Patterson
CPC分类号： G01R31/2884
摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.
摘要翻译： 使用其检测缺陷的测试结构和方法。 包括第一，第二和第三探针焊盘的可探测电压对比度（VC）梳状测试结构，包括接地尖齿的梳状结构，接地尖端之间的浮动尖齿，与每个浮动齿的端部耦合的开关装置， 以及将所述浮动尖齿连接到所述第二探针焊盘，并且所述第三探针焊盘是控制所述切换装置的控制焊盘。 一种可探测的VC蛇形测试结构，包括第一，第二，第三和第四探针焊盘，包括接地尖齿的梳状结构，接地尖齿之间的浮动尖齿和连接在第二和第三探针焊盘之间的每个浮动齿，切换 连接到每个浮动齿的端部并且将浮动尖齿连接到第二和第三探针焊盘的装置，第四探针焊盘是控制开关装置的控制焊盘。
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公开(公告)号：US07518190B2
公开(公告)日：2009-04-14
申请号：US11308408
申请日：2006-03-22
IPC分类号： H01L23/62
CPC分类号： H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.
摘要翻译： 公开了用于在绝缘体上硅（SOI）衬底上接地栅叠层和/或硅有源区前线结构的结构和方法，其可用作VC检验的测试结构。 在一个实施例中，结构包括其上具有SOI衬底的接地体硅衬底，SOI衬底包括绝缘体上硅（SOI）层和掩埋氧化物（BOX）层; 所述硅有源区在所述SOI层内具有至少一个指状元件，所述至少一个指状元件由浅沟槽隔离（STI）层隔离; 以及与所述至少一个指状元件相交并且穿过所述STI层和所述BOX层延伸到所述接地体硅衬底的多晶硅地，所述多晶硅接地与所述硅有源区和所述接地体硅衬底接触。
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23.发明授权Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 有权内部去耦电容器，制造和测试电路的方法公开(公告)号：US07323382B2
公开(公告)日：2008-01-29
申请号：US11707060
申请日：2007-02-16
IPC分类号： H01L21/8242
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译： 为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。 可以在两个图案之间提供高介电常数材料。 还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。
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公开(公告)号：US07195971B2
公开(公告)日：2007-03-27
申请号：US11066738
申请日：2005-02-28
IPC分类号： H01L21/8242
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译： 为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。 可以在两个图案之间提供高介电常数材料。 还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。
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25.发明授权Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 有权内部去耦电容器，制造和测试电路的方法公开(公告)号：US06677637B2
公开(公告)日：2004-01-13
申请号：US09330803
申请日：1999-06-11
IPC分类号： H01C2992
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译： 为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。 可以在两个图案之间提供高介电常数材料。 还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。
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26.发明授权
公开(公告)号：US5308438A
公开(公告)日：1994-05-03
申请号：US828054
申请日：1992-01-30
IPC分类号： B24B37/013 , B24B49/16 , H01L21/3105 , H01L21/304
CPC分类号： B24B37/013 , B24B49/16 , H01L21/31053
摘要： An apparatus and method for determining a selected endpoint in the polishing of layers on a workpiece in a chemical/mechanical polishing apparatus where the workpiece is rotated by a motor against a polishing pad. When a difficult to polish layer, i.e., one requiring a chemical change in a surface skin of the layer which skin is then abraded away by a mechanical process is removed from a more easy to polish surface, i.e., one that relies solely on mechanical abrasion and does not need to have a chemically converted skin thereon. The power required to maintain a set rotational speed in a motor rotating the workpiece significantly drops when the difficult to polish layer is removed. This current drop is used to detect the point at which the polishing must be stopped to avoid over polishing effects, i.e., dishing or thinning or removal of the more easily removed underlying material. Thus, an end point in the process can be established.
摘要翻译： 一种用于确定在化学/机械抛光装置中的工件上的层的抛光中的选定端点的装置和方法，其中工件通过电机旋转抵靠抛光垫。 当难以抛光的层，即需要在层的表面皮肤中化学变化的层，然后通过机械方法将皮肤磨损掉，从更容易的抛光表面去除，即仅依赖于机械磨损的表面 并且不需要在其上具有化学转化的皮肤。 当去除难抛光层时，在旋转工件的电机中保持设定转速所需的功率显着下降。 该电流下降用于检测必须停止抛光的点以避免抛光效应，即，更容易去除的下层材料的凹陷或变薄或去除。 因此，可以建立该过程中的终点。
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公开(公告)号：US4919750A
公开(公告)日：1990-04-24
申请号：US342616
申请日：1989-04-24
申请人： Robert C. Bausmith , William J. Cote , John E. Cronin , Karey L. Holland , Carter W. Kaanta , Pei-Ing P. Lee , Terrance M. Wright
发明人： Robert C. Bausmith , William J. Cote , John E. Cronin , Karey L. Holland , Carter W. Kaanta , Pei-Ing P. Lee , Terrance M. Wright
IPC分类号： C23F4/00 , H01L21/3213
CPC分类号： C23F4/00 , H01L21/32136
摘要： A method for dry etching metals that form low volatility chlordes, in which Z-Cl reaction products are controllably introduced into a conventional Cl-based plasma independent of the workpiece. The Z-Cl products (e.g., AlCl.sub.3, GaCl.sub.3, etc.) are metal chlorides that have both electron acceptor and chloride donor properties. Thus, metals M (e.g., cobalt, copper and nickel) that usually produce low volatility chlorides can be controllably complexed to form high volatility Z.sub.x Cl.sub.y M.sub.z reaction products.
摘要翻译： 用于干蚀刻形成低挥发性氯的金属的方法，其中Z-Cl反应产物可以独立于工件被可控地引入到常规的基于Cl的等离子体中。 Z-Cl产物（例如，AlCl 3，GaCl 3等）是具有电子受体和氯化物给体性质的金属氯化物。 因此，通常产生低挥发性氯化物的金属M（例如钴，铜和镍）可以可控地复合以形成高挥发性Z x ClyMz反应产物。
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公开(公告)号：US4786360A
公开(公告)日：1988-11-22
申请号：US31813
申请日：1987-03-30
IPC分类号： C23F4/00 , H01L21/3213 , B44C1/22
CPC分类号： C23F4/00 , H01L21/32136
摘要： A method for anisotropically etching a thick tungsten layer atop a thin underlayer comprised of titanium nitride, by exposure to a gaseous plasma comprised of a binary mixture of chlorine gas and oxygen, wherein oxygen comprises approximately 25%-45% of the mixture by volume. This plasma provides a combination of high tungsten etch rate, highly uniform etching, anisotropic profiles, and high etch rate ratio to underlaying glass passivation layers.
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公开(公告)号：US20120319716A1
公开(公告)日：2012-12-20
申请号：US13593975
申请日：2012-08-24
申请人： William J. Cote , Yi Feng , Oliver D. Patterson
发明人： William J. Cote , Yi Feng , Oliver D. Patterson
IPC分类号： G01R1/067
CPC分类号： G01R31/2884
摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.
摘要翻译： 使用其检测缺陷的测试结构和方法。 包括第一，第二和第三探针焊盘的可探测电压对比度（VC）梳状测试结构，包括接地尖齿的梳状结构，接地尖端之间的浮动尖齿，与每个浮动齿的端部耦合的开关装置， 以及将所述浮动尖齿连接到所述第二探针焊盘，并且所述第三探针焊盘是控制所述切换装置的控制焊盘。 一种可探测的VC蛇形测试结构，包括第一，第二，第三和第四探针焊盘，包括接地尖齿的梳状结构，接地尖齿之间的浮动尖齿和连接在第二和第三探针焊盘之间的每个浮动齿，切换 连接到每个浮动齿的端部并且将浮动尖齿连接到第二和第三探针焊盘的装置，第四探针焊盘是控制开关装置的控制焊盘。
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公开(公告)号：US07732866B2
公开(公告)日：2010-06-08
申请号：US12348438
申请日：2009-01-05
IPC分类号： H01L23/62
CPC分类号： H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.
摘要翻译： 公开了用于在绝缘体上硅（SOI）衬底上接地栅叠层和/或硅有源区前线结构的结构和方法，其可用作VC检验的测试结构。 在一个实施例中，结构包括其上具有SOI衬底的接地体硅衬底，SOI衬底包括绝缘体上硅（SOI）层和掩埋氧化物（BOX）层; 所述硅有源区在所述SOI层内具有至少一个指状元件，所述至少一个指状元件由浅沟槽隔离（STI）层隔离; 以及与所述至少一个指状元件相交并且穿过所述STI层和所述BOX层延伸到所述接地体硅衬底的多晶硅地，所述多晶硅接地与所述硅有源区和所述接地体硅衬底接触。
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