Human-to-mobile interfaces
    21.
    发明申请
    Human-to-mobile interfaces 有权
    人到手机界面

    公开(公告)号:US20090055732A1

    公开(公告)日:2009-02-26

    申请号:US11887019

    申请日:2006-03-23

    IPC分类号: G06F17/21

    摘要: A method of for a mobile telephone data input apparatus comprising a plurality of data input keys having multi-character indicia, said method adapted to facilitate a reduction in the number of user interactions required to create a given data string to less than the number of characters within said data string, the method comprising the following steps: storing a set of data strings each with a priority indicator associated therewith, wherein the indicator is a measure of a plurality of derivatives associated with the data string; recognising an event; looking up the most likely subsequent data string to follow the event from the set of data strings based on one or more of the plurality of derivatives; ordering the data strings for display based on the priority indicator of that data string; if the required subsequent data string is included in the list selecting the required subsequent data string; if the required subsequent data string is not included in the list entering a event and repeating steps b to e; updating the priority indicator of the selected data string; updating the set of data strings based on the updated priority indicator.

    摘要翻译: 一种用于包括具有多字符标记的多个数据输入键的移动电话数据输入装置的方法,所述方法适于有助于将创建给定数据串所需的用户交互次数减少到少于字符数 在所述数据串中,所述方法包括以下步骤:存储每组具有与其相关联的优先级指示符的数据串集合,其中所述指示符是与所述数据串相关联的多个导数的度量; 承认事件; 从所述多个导数中的一个或多个的数据串集合中查找最可能的后续数据串以跟随事件; 根据该数据串的优先级指示器对数据串进行排序; 如果所需的后续数据串被包括在选择所需的后续数据串的列表中; 如果所需的后续数据字符串不包括在输入事件的列表中并重复步骤b至e; 更新所选数据串的优先级指示符; 基于更新的优先级指示符更新数据串集合。

    Low Overhead Access to Shared On-Chip Hardware Accelerator With Memory-Based Interfaces
    22.
    发明申请
    Low Overhead Access to Shared On-Chip Hardware Accelerator With Memory-Based Interfaces 有权
    具有基于内存接口的共享片上硬件加速器的低架构访问

    公开(公告)号:US20080222396A1

    公开(公告)日:2008-09-11

    申请号:US11684348

    申请日:2007-03-09

    IPC分类号: G06F9/50

    摘要: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.

    摘要翻译: 在一个实施例中,预期了一种方法。 用户特权线程请求访问硬件加速器。 通过响应请求的较高特权线程向硬件加速器的访问授予用户特权线程。 一个或多个命令由用户特权的线程传送到硬件加速器,而不受较高特权线程的干扰,并响应于授权的访问。 一个或多个命令使硬件加速器执行一个或多个任务。 计算机可读介质包括当各种实施例中被执行时实施该方法的部分的指令,以及硬件加速器和耦合到硬件加速器的处理器。

    PRESS FABRIC SEAM AREA
    23.
    发明申请
    PRESS FABRIC SEAM AREA 失效
    新闻社区

    公开(公告)号:US20080190580A1

    公开(公告)日:2008-08-14

    申请号:US11673085

    申请日:2007-02-09

    IPC分类号: D21F3/00

    摘要: A pinseam press fabric is smoothed in the area of the seam by depositing polyurethane particles having a size of about 1 to 500 micrometers across the seam of the felt defined by the ends of the fabric. The polyurethane particles are drawn into the seam end by the application of a vacuum. Once the particles are deposited, the fabric is heated so that the polyurethane particles melt to form a polymeric matrix.

    摘要翻译: 通过在由织物的端部限定的毡的接缝上沉积约1至500微米尺寸的聚氨酯颗粒,在接缝区域中平滑针刺压榨织物。 通过施加真空将聚氨酯颗粒拉入接缝端。 一旦颗粒沉积,织物被加热,使得聚氨酯颗粒熔化形成聚合物基体。

    Method and apparatus for primary cache tag error handling
    24.
    发明授权
    Method and apparatus for primary cache tag error handling 有权
    用于主缓存标签错误处理的方法和装置

    公开(公告)号:US07310709B1

    公开(公告)日:2007-12-18

    申请号:US11100997

    申请日:2005-04-06

    IPC分类号: G06F11/00 G06F12/00 G06F12/08

    摘要: A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary cache to the secondary cache. In response to the tag parity packet, each tag entry in the secondary cache that is associated with the parity error is invalidated. Upon receiving an acknowledgment of receipt of the tag parity packet, the primary cache functions to invalidate each tag entry in the primary cache that is associated with the parity error. Then, the secondary cache communicates data requested in the load instruction to the primary cache.

    摘要翻译: 公开了一种用于在基于目录的高速缓存系统中的一级高速缓存和二级高速缓存之间维持一致性的方法和装置。 一旦识别出一次高速缓存中的奇偶校验错误,就从主缓存发送标签奇偶校验分组和加载指令给二级缓存。 响应于标签奇偶校验分组,与奇偶校验错误相关联的辅助高速缓存中的每个标签条目无效。 在接收到标签奇偶校验分组的接收的确认之后,主缓存功能使得与奇偶校验错误相关联的主缓存中的每个标签条目无效。 然后,二级缓存将加载指令中请求的数据传送到主缓存。

    Method and apparatus for testing data steering logic for data storage having independently addressable subunits
    25.
    发明申请
    Method and apparatus for testing data steering logic for data storage having independently addressable subunits 有权
    用于测试具有独立可寻址子单元的数据存储的数据转向逻辑的方法和装置

    公开(公告)号:US20070220378A1

    公开(公告)日:2007-09-20

    申请号:US11367959

    申请日:2006-03-03

    IPC分类号: G11C29/00

    摘要: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

    摘要翻译: 通过为存储器阵列存储位置的每个可寻址子单元提供数据总线通道来测试存储器阵列的I / O中的读写数据转向逻辑。 每个总线通道连接到比较器的数据输入。 BIST控制器通过写入指导逻辑将测试模式写入存储器,并并行读取测试模式以测试写入转向逻辑。 BIST控制器将测试模式并行地写入存储器,并通过读取转向逻辑读取测试模式,以测试读取转向逻辑。 在这两种情况下,专用于每个总线通道的单独的比较器验证子数据在数据总线通道和存储器存储位置子单元之间正确移位。 比较器在正常操作期间被有效地禁用,以防止逻辑门切换。

    Human-to-Computer Interfaces
    26.
    发明申请
    Human-to-Computer Interfaces 有权
    人机界面

    公开(公告)号:US20070216651A1

    公开(公告)日:2007-09-20

    申请号:US10593833

    申请日:2005-03-23

    申请人: Sanjay Patel

    发明人: Sanjay Patel

    IPC分类号: G06F3/023

    CPC分类号: G06F3/0237

    摘要: The invention relates to an improved keyboard and keyboard driver for facilitating a reduction in the number of key presses required to create or delete a given data string (i.e. mnemonics, abbreviations, words, sentences, paragraphs etc.). The keyboard includes an array of keys having multi-character indicia and an interface system comprising data storage means; data processing means; and data display means, wherein the data processing means reduces key presses by filtering data stored within the data storage means by initial character, as determined by the character or characters ascribed to a data input key initially pressed by a user, and prioritizing the filtered data in real-time according to user-configurable prioritization parameters (using qualitative and/or quantitative information relating to each data string stored within the storage means). The invention also provides improved calculator functionality and function-lock keys. Taken together, the keyboard and keyboard driver of the invention (which may be implemented in isolation or together) promotes ease of use, reduced user-interactivity, elevated efficiency and thus enhanced productivity that in turn yields improved accuracy and flexibility.

    摘要翻译: 本发明涉及一种改进的键盘和键盘驱动程序,用于便于减少创建或删除给定数据串(即助记符,缩略语,单词,句子,段落等)所需的按键数量。 键盘包括具有多字符标记的键阵列和包括数据存储装置的接口系统; 数据处理手段; 数据显示装置,其中数据处理装置通过按照初始字符过滤存储在数据存储装置中的数据来减少按键,如由由用户最初按压的数据输入键所决定的字符或字符所确定的,并且对经过滤数据进行优先排序 根据用户可配置的优先级参数(使用与存储在存储装置中的每个数据串相关的定性和/或定量信息)实时地进行。 本发明还提供改进的计算器功能和功能锁定键。 综合起来,本发明的键盘和键盘驱动器(其可以隔离或一起实现)促进易于使用,减少的用户交互性,提高的效率并因此提高了生产率,从而提高了精度和灵活性。

    Through air dryer fabric
    27.
    发明授权
    Through air dryer fabric 失效
    通过空气干燥器织物

    公开(公告)号:US07207356B2

    公开(公告)日:2007-04-24

    申请号:US11131987

    申请日:2005-05-18

    IPC分类号: D21F7/08 D03D25/00

    摘要: A through-air dryer (TAD) fabric formed by interweaving of a warp yarn system with a weft yarn system. The TAD fabric has a paper side with a contact area between 20% and 30%. The warp yarn system includes flat warp yarns and/or the weft yarn system includes flat weft yarns which have not been subjected to a sanding process after weaving of the fabric and which have an aspect ratio of 1.15:1 to 1.35:1.

    摘要翻译: 由经纱系统与纬纱系统交织而形成的通风干燥机(TAD)织物。 TAD织物具有接触面积在20%至30%之间的纸面。 经纱系统包括扁平经纱和/或纬纱系统包括在编织织物之后未经过磨砂加工并且具有1.15:1至1.35:1的纵横比的扁平纬纱。

    Method and apparatus for resolving multiple branches
    29.
    发明授权
    Method and apparatus for resolving multiple branches 失效
    用于解决多个分支的方法和装置

    公开(公告)号:US06256729B1

    公开(公告)日:2001-07-03

    申请号:US09004971

    申请日:1998-01-09

    IPC分类号: G06F1500

    CPC分类号: G06F9/3861 G06F9/3806

    摘要: A method for repairing a pipeline in response to a branch instruction having a branch, includes the steps of providing a branch repair table having a plurality of entries, allocating an entry in the branch repair table for the branch instruction, storing a target address, a fall-through address, and repair information in the entry in the branch repair table, processing the branch instruction to determine whether the branch was taken, and repairing the pipeline in response to the repair information and the fall-through address in the entry in the branch repair table when the branch was not taken.

    摘要翻译: 一种用于响应于具有分支的分支指令来修复流水线的方法,包括以下步骤:提供具有多个条目的分支修复表,在分支指令的分支修复表中分配条目,存储目标地址, 分支修复表中的条目中的修复信息和修复信息,处理分支指令以确定是否采用分支,以及修复管道,以响应修复信息和条目中的到达地址 分支修复表时未分支。

    Bar engine brake
    30.
    发明授权
    Bar engine brake 失效
    酒吧发动机制动

    公开(公告)号:US6085721A

    公开(公告)日:2000-07-11

    申请号:US145243

    申请日:1998-09-02

    IPC分类号: F01L13/06 F02D13/04

    CPC分类号: F01L13/06

    摘要: The present invention is directed to a control system for controlling operation of an engine compression release brake for an engine. The control system includes a valve actuation assembly for actuating at least one valve during a predetermined engine operating condition. The control system also includes an energy supply assembly for supplying energy to operate the valve actuation assembly. The control system includes a control assembly for controlling the operation of valve actuation assembly.

    摘要翻译: 本发明涉及一种用于控制用于发动机的发动机压缩释放制动器的操作的控制系统。 控制系统包括用于在预定发动机操作状态期间致动至少一个阀的阀致动组件。 控制系统还包括用于提供能量以操作阀致动组件的能量供应组件。 控制系统包括用于控制阀致动组件的操作的控制组件。