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137 条记录 (耗时 0.041 秒)

    Method and apparatus for primary cache tag error handling
    1.
    发明授权
    Method and apparatus for primary cache tag error handling 有权
    用于主缓存标签错误处理的方法和装置

    公开(公告)号：US07310709B1

    公开(公告)日：2007-12-18

    申请号：US11100997

    申请日：2005-04-06

    申请人： Kathirgamar Aingaran ,  Ramaswamy Sivaramakrishnan ,  Sanjay Patel

    发明人： Kathirgamar Aingaran ,  Ramaswamy Sivaramakrishnan ,  Sanjay Patel

    IPC分类号： G06F11/00 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0817 ,  G06F11/1064 ,  G06F12/0822 ,  G06F12/0891 ,  G06F2212/1032

    摘要： A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary cache to the secondary cache. In response to the tag parity packet, each tag entry in the secondary cache that is associated with the parity error is invalidated. Upon receiving an acknowledgment of receipt of the tag parity packet, the primary cache functions to invalidate each tag entry in the primary cache that is associated with the parity error. Then, the secondary cache communicates data requested in the load instruction to the primary cache.

    摘要翻译： 公开了一种用于在基于目录的高速缓存系统中的一级高速缓存和二级高速缓存之间维持一致性的方法和装置。 一旦识别出一次高速缓存中的奇偶校验错误，就从主缓存发送标签奇偶校验分组和加载指令给二级缓存。 响应于标签奇偶校验分组，与奇偶校验错误相关联的辅助高速缓存中的每个标签条目无效。 在接收到标签奇偶校验分组的接收的确认之后，主缓存功能使得与奇偶校验错误相关联的主缓存中的每个标签条目无效。 然后，二级缓存将加载指令中请求的数据传送到主缓存。

    System and method for block write to memory
    2.
    发明授权
    System and method for block write to memory 有权
    用于块写入存储器的系统和方法

    公开(公告)号：US07281096B1

    公开(公告)日：2007-10-09

    申请号：US11054850

    申请日：2005-02-09

    申请人： Ramaswamy Sivaramakrishnan ,  Sunil Vemula ,  Sanjay Patel ,  James P. Laudon

    发明人： Ramaswamy Sivaramakrishnan ,  Sunil Vemula ,  Sanjay Patel ,  James P. Laudon

    IPC分类号： G06F13/14

    CPC分类号： G06F12/0802 ,  G06F9/30047 ,  G06F9/383 ,  Y02D10/13

    摘要： A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

    摘要翻译： 提供了一种用于将数据写入高速缓存的硬件实现方法。 在该硬件实现方法中，接收到块初始化存储（BIS）指令以将数据从处理器核心写入存储器块。 BIS指令包括来自处理器核心的数据。 此后，将虚拟读取请求发送到存储器控制器，并且从存储器控制器接收已知的数据，而不访问主存储器。 然后将已知数据写入高速缓存，并且在已知数据被写入之后，来自处理器核心的数据被写入高速缓存。 还描述了用于将数据写入缓存的系统和处理器。

    Apparatus and method for guest and root register sharing in a virtual machine
    5.
    发明授权
    Apparatus and method for guest and root register sharing in a virtual machine 有权
    在虚拟机中访客和根寄存器共享的装置和方法

    公开(公告)号：US09086906B2

    公开(公告)日：2015-07-21

    申请号：US13436654

    申请日：2012-03-30

    申请人： Sanjay Patel ,  Ranjit Joseph Rozario

    发明人： Sanjay Patel ,  Ranjit Joseph Rozario

    IPC分类号： G06F9/455

    CPC分类号： G06F9/4555

    摘要： A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

    摘要翻译： 计算机可读存储介质包括可执行指令，以定义具有访客模式控制寄存器的处理器，所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定 访客模式控制寄存器包括一个控制位，用于指定访客阻止寄存器状态和共享寄存器状态。 根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。 根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。 访客环境和根本环境支持硬件资源的虚拟化，使得支持多个应用的​​多个操作系统由硬件资源执行。

    Nanonized Iron Compositions and Methods of Use Thereof
    7.
    发明申请
    Nanonized Iron Compositions and Methods of Use Thereof 审中-公开
    纳米铁组合物及其使用方法

    公开(公告)号：US20120177700A1

    公开(公告)日：2012-07-12

    申请号：US13338210

    申请日：2011-12-27

    申请人： Mir A. Imran ,  Mir Hashim ,  Lu Wang ,  Sanjay Patel ,  Joel M. Harris ,  Phil Morgan

    发明人： Mir A. Imran ,  Mir Hashim ,  Lu Wang ,  Sanjay Patel ,  Joel M. Harris ,  Phil Morgan

    IPC分类号： A61K9/00 ,  A61K33/42 ,  B82Y5/00

    CPC分类号： A61K9/14 ,  A61K33/26

    摘要： Embodiments of the invention provide nanonized iron compositions for treatment of iron deficiency such as iron deficiency anemia. Many embodiments provide nanonized iron compositions which are sized to minimize adverse reaction such as immune response, adverse GI reaction and allergic reaction to iron compound included in the composition. The nanonized iron compositions can be used in a variety of drug delivery forms, including an oral dosage form, a transdermal patch, in an intravenous solution or in a dialysate for treatment of a patient with chronic kidney disease (CKD). Embodiments of the invention also provide methods of using the nanonized iron compositions for the treatment of iron deficiency in a patient in need thereof including patients with iron deficiency anemia and CKD.

    摘要翻译： 本发明的实施方案提供了用于治疗铁缺乏症（例如缺铁性贫血）的纳米铁组合物。 许多实施方案提供纳米级铁组合物，其尺寸设定成使包括在组合物中的铁化合物的不良反应如免疫应答，不良GI反应和过敏反应最小化。 纳米铁组合物可以以各种药物递送形式使用，包括口服剂型，透皮贴剂，静脉内溶液或用于治疗慢性肾脏病（CKD）患者的透析液。 本发明的实施方案还提供了使用纳米铁组合物治疗需要其的患者缺铁的方法，包括缺铁性贫血和CKD患者。

    Resource sharing to reduce implementation costs in a multicore processor
    8.
    发明授权
    Resource sharing to reduce implementation costs in a multicore processor 有权
    资源共享以降低多核处理器中的实施成本

    公开(公告)号：US08195883B2

    公开(公告)日：2012-06-05

    申请号：US12694877

    申请日：2010-01-27

    申请人： Prashant Jain ,  Yoganand Chillarige ,  Sandip Das ,  Shukur Moulali Pathan ,  Srinivasan R. Iyengar ,  Sanjay Patel

    发明人： Prashant Jain ,  Yoganand Chillarige ,  Sandip Das ,  Shukur Moulali Pathan ,  Srinivasan R. Iyengar ,  Sanjay Patel

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0811 ,  G06F12/0813

    摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

    摘要翻译： 处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。 控制器可以共享对耦合到互连网络的互连出口端口的访问，并且可以生成多个并发请求以经由共享端口传送数据，其中每个请求去往相应的核心，并且其中端口的数据路径宽度 小于多个请求的组合宽度。 给定标签单元可以在控制器之间仲裁以访问共享端口，使得请求被串行地发送到相应的核心而不是同时发送。

    High speed semiconductor optical modulator
    10.
    发明授权
    High speed semiconductor optical modulator 有权
    高速半导体光调制器

    公开(公告)号：US07672553B2

    公开(公告)日：2010-03-02

    申请号：US11681070

    申请日：2007-03-01

    申请人： Douglas M. Gill ,  Christopher D. W. Jones ,  Sanjay Patel ,  Mahmoud Rasras ,  Nils G. Weimann

    发明人： Douglas M. Gill ,  Christopher D. W. Jones ,  Sanjay Patel ,  Mahmoud Rasras ,  Nils G. Weimann

    IPC分类号： G02B6/26

    CPC分类号： G02F1/025 ,  G02F2001/0152

    摘要： The present invention provides an optical waveguide modulator. In one embodiment, the optical waveguide modulator includes a semiconductor planar optical waveguide core and doped semiconductor connecting paths located adjacent opposite sides of the core and capable of applying a voltage across the core. The optical waveguide core and connecting paths form a structure having back-to-back PN semiconductor junctions. In another embodiment, the optical waveguide modulator includes a semiconductor optical waveguide core including a ridge portion wherein the ridge portion has at least one PN semiconductor junction located therein. The optical waveguide modulator also includes one or more doped semiconductor connecting paths located laterally adjacent the ridge portion and capable of applying a voltage to the ridge portion.

    摘要翻译： 本发明提供一种光波导调制器。 在一个实施例中，光波导调制器包括半导体平面光波导芯和与芯相邻的相邻侧面的掺杂半导体连接路径，并能跨越芯施加电压。 光波导芯和连接路径形成具有背对背PN半导体结的结构。 在另一个实施例中，光波导调制器包括半导体光波导芯，其包括脊部，其中脊部具有位于其中的至少一个PN半导体结。 光波导调制器还包括一个或多个掺杂的半导体连接路径，其位于横向邻近脊部分并且能够向脊部分施加电压。