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公开(公告)号：US06256729B1
公开(公告)日：2001-07-03
申请号：US09004971
申请日：1998-01-09
IPC分类号： G06F1500
CPC分类号： G06F9/3861 , G06F9/3806
摘要： A method for repairing a pipeline in response to a branch instruction having a branch, includes the steps of providing a branch repair table having a plurality of entries, allocating an entry in the branch repair table for the branch instruction, storing a target address, a fall-through address, and repair information in the entry in the branch repair table, processing the branch instruction to determine whether the branch was taken, and repairing the pipeline in response to the repair information and the fall-through address in the entry in the branch repair table when the branch was not taken.
摘要翻译： 一种用于响应于具有分支的分支指令来修复流水线的方法，包括以下步骤：提供具有多个条目的分支修复表，在分支指令的分支修复表中分配条目，存储目标地址， 分支修复表中的条目中的修复信息和修复信息，处理分支指令以确定是否采用分支，以及修复管道，以响应修复信息和条目中的到达地址 分支修复表时未分支。
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2.发明授权公开(公告)号：US06289441B1
公开(公告)日：2001-09-11
申请号：US09005076
申请日：1998-01-09
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/3806 , G06F9/3844
摘要： A method and apparatus for performing multiple branch predictions per cycle is disclosed. The method and apparatus according to the present invention determine, within one fetch cycle, which instructions in a plurality of fetch instructions are branches and whether such branches are taken or not taken thereby finding the oldest taken branch, which has a target address that is fetched within the same fetch cycle.
摘要翻译： 公开了一种用于每个周期执行多个分支预测的方法和装置。 根据本发明的方法和装置在一个读取周期内确定多个获取指令中的哪些指令是分支，以及是否采用这样的分支，从而找到具有获取的目标地址的最早的分支 在相同的获取周期内。
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公开(公告)号：US5938761A
公开(公告)日：1999-08-17
申请号：US976826
申请日：1997-11-24
CPC分类号： G06F9/3806
摘要： One embodiment of the present invention provides a method and an apparatus for predicting the target of a branch instruction. This method and apparatus operate by using a translation lookaside buffer (TLB) to store page numbers for predicted branch target addresses. In this embodiment, a branch target address table stores a small index to a location in the translation lookaside buffer, and this index is used retrieve a page number from the location in the translation lookaside buffer. This page number is used as the page number portion of a predicted branch target address. Thus, a small index into a translation lookaside buffer can be stored in a predicted branch target address table instead of a larger page number for the predicted branch target address. This technique effectively reduces the size of a predicted branch target table by eliminating much of the space that is presently wasted storing redundant page numbers. Another embodiment maintains coherence between the branch target address table and the translation lookaside buffer. This makes it possible to detect a miss in the translation lookaside buffer at least one cycle earlier by examining the branch target address table.
摘要翻译： 本发明的一个实施例提供了一种用于预测分支指令的目标的方法和装置。 该方法和装置通过使用翻译后备缓冲器（TLB）来存储用于预测的分支目标地址的页码。 在本实施例中，分支目标地址表将小索引存储到翻译后备缓冲器中的位置，并且使用该索引从翻译后备缓冲器中的位置检索页码。 该页码用作预测分支目标地址的页码部分。 因此，可以在预测的分支目标地址表中存储向翻译后备缓冲器的小索引，而不是预测的分支目标地址的较大的页码。 该技术通过消除存储冗余页码的目前浪费的大部分空间来有效地减小预测分支目标表的大小。 另一个实施例维护分支目标地址表和转换后备缓冲器之间的一致性。 这使得可以通过检查分支目标地址表来更早地检测翻译后备缓冲区中的未命中至少一个周期。
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公开(公告)号：US5854761A
公开(公告)日：1998-12-29
申请号：US883544
申请日：1997-06-26
CPC分类号： G11C7/00 , G06F12/0864 , G06F12/0886 , G11C7/1042
摘要： A cache memory array stores two-way set associative data. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.
摘要翻译： 缓存存储器阵列存储双向组关联数据。 奇数组数据组存储奇数组合的双向组关联数据，其中每个奇数组的两种方式在奇数组数据库内水平排列。 偶数集数据库存储偶数集合的双向组关联数据，其中每个偶数集合的两个方式在偶数集数据库内水平对准。 此外，奇数组数据组与偶数组数据组水平对准，使得每个奇数组都与下一个偶数组水平对准。 水平对齐的方式被交织以减少数据路径宽度。 设置和路径选择电路从数组中提取数据行。 阵列可以在结构上由单端口RAM单元实现。
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5.发明授权Method for storing data in two-way set associative odd and even banks of a cache memory 失效用于将数据存储在高速缓冲存储器的双向组相关奇偶组中的方法公开(公告)号：US06256709B1
公开(公告)日：2001-07-03
申请号：US08883543
申请日：1997-06-26
IPC分类号： G06R1202
CPC分类号： G06F12/0864
摘要： Two-way set associative data is stored in a cache memory array. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.
摘要翻译： 双向组关联数据存储在高速缓存存储器阵列中。 奇数组数据组存储奇数组合的双向组关联数据，其中每个奇数组的两种方式在奇数组数据库内水平排列。 偶数集数据库存储偶数集合的双向组关联数据，其中每个偶数集合的两个方式在偶数集数据库内水平对准。 此外，奇数组数据组与偶数组数据组水平对准，使得每个奇数组都与下一个偶数组水平对准。 水平对齐的方式被交织以减少数据路径宽度。 设置和路径选择电路从数组中提取数据行。 阵列可以在结构上由单端口RAM单元实现。
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6.发明授权
公开(公告)号：US6115810A
公开(公告)日：2000-09-05
申请号：US154007
申请日：1998-09-16
CPC分类号： G06F9/3848
摘要： One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction stream. This system receives a current address specifying an address of a current instruction. It uses this current address (or possibly a preceding address) to generate a first select signal, which is used to select a first predicted address of an instruction following the current instruction in the computer instruction stream. At the same time the system generates a second select signal, which takes more time to generate than the first select signal but achieves a more accurate selection for a predicted address of the instruction following the current instruction. The system assumes that the first predicted address is correct and proceeds with a subsequent instruction fetch operation using the first predicted address. Next, the system compares the first select signal with the second select signal. If the first select signal is the same as the second select signal, the system allows the subsequent instruction fetch operation to proceed using the first predicted address. Otherwise, the system uses the second select signal to select a second predicted address, and delays the subsequent instruction fetch operation so that the instruction fetch operation can proceed using the second predicted address. This bi-level architecture allows branch prediction work efficiently even at the higher clock frequencies that arise as semiconductor technologies continue to improve.
摘要翻译： 本发明的一个实施例提供了一种用于在计算机指令流中的分支指令之后预测指令的地址的系统。 该系统接收指定当前指令的地址的当前地址。 它使用该当前地址（或可能的是前一地址）产生第一选择信号，该第一选择信号用于选择在计算机指令流中的当前指令之后的指令的第一预测地址。 同时，系统产生第二选择信号，其比第一选择信号花费更多的时间来生成，但是对于当前指令之后的指令的预测地址实现更精确的选择。 系统假设第一预测地址是正确的，并且使用第一预测地址进行随后的指令获取操作。 接下来，系统将第一选择信号与第二选择信号进行比较。 如果第一选择信号与第二选择信号相同，则系统允许随后的指令提取操作使用第一预测地址进行。 否则，系统使用第二选择信号来选择第二预测地址，并延迟后续指令提取操作，以便使用第二预测地址进行指令获取操作。 这种双级架构允许分支预测有效地工作，即使在半导体技术不断改进时产生的较高时钟频率。
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公开(公告)号：US6134654A
公开(公告)日：2000-10-17
申请号：US154789
申请日：1998-09-16
CPC分类号： G06F9/3806 , G06F9/3848
摘要： One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction stream. This system concurrently performs a fast single-cycle branch prediction operation to produce a first predicted address, and a more-accurate multiple-cycle branch prediction operation to produce a second predicted address. The system assumes that the first predicted address is correct and proceeds with a subsequent instruction fetch operation using the first predicted address. If the first predicted address is the same as the second predicted address, the subsequent instruction fetch operation is allowed to proceed using the first predicted address. Otherwise, the subsequent fetch operation is delayed so that it can proceed using the second predicted address. In this way, the system will typically perform a fast instruction fetch operation using the first predicted address, and will less frequently have to wait for the more-accurate second predicted address. This bi-level architecture allows branch prediction work efficiently even at the higher clock frequencies that arise as semiconductor technologies continue to improve. In accordance with one feature of the above embodiment, the multiple-cycle branch prediction operation involves selecting the second predicted address from between a branch target address, a next sequential address and a return address from a function call. In accordance with another feature, the second predicted address is selected using information from a branch type table, which contains information specifying the type of branch instructions located at particular addresses.
摘要翻译： 本发明的一个实施例提供了一种用于在计算机指令流中的分支指令之后预测指令的地址的系统。 该系统同时执行快速的单周期分支预测操作，以产生第一预测地址和更准确的多周期分支预测操作，以产生第二预测地址。 系统假设第一预测地址是正确的，并且使用第一预测地址进行随后的指令获取操作。 如果第一预测地址与第二预测地址相同，则允许随后的指令获取操作使用第一预测地址进行。 否则，后续的提取操作被延迟，使得它可以使用第二预测地址进行。 以这种方式，系统通常将使用第一预测地址执行快速指令获取操作，并且将更不频繁地等待更准确的第二预测地址。 这种双级架构允许分支预测有效地工作，即使在半导体技术不断改进时产生的较高时钟频率。 根据上述实施例的一个特征，多周期分支预测操作包括从分支目标地址，下一个顺序地址和来自函数调用的返回地址之间选择第二预测地址。 根据另一特征，使用来自分支类型表的信息选择第二预测地址，分支类型表包含指定位于特定地址的分支指令的类型的信息。
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8.发明授权Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures 有权包括提取单元的装置，包括分支历史信息以增加多流水线分支预测结构的性能公开(公告)号：US06330662B1
公开(公告)日：2001-12-11
申请号：US09256623
申请日：1999-02-23
IPC分类号： G06F930
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/3848
摘要： An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the next fetch address mechanism generating a next fetch address for a fetch bundle over at least two cycles of the processor. The next fetch address mechanism determines the next fetch address based on whether a control transfer instruction from an intermediate set of fetched instructions is taken.
摘要翻译： 一个指令提取单元，用于从处理器的指令高速缓存中取出指令。 提取单元包括产生预测的下一个提取地址的下一个提取地址机制，下一个提取地址机制在处理器的至少两个周期上产生用于获取束的下一个提取地址。 下一个提取地址机制基于取得的指令的中间集合的控制传输指令是否取决于下一个提取地址。
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9.发明申请Low Overhead Access to Shared On-Chip Hardware Accelerator With Memory-Based Interfaces 有权具有基于内存接口的共享片上硬件加速器的低架构访问公开(公告)号：US20080222396A1
公开(公告)日：2008-09-11
申请号：US11684348
申请日：2007-03-09
申请人： Lawrence A. Spracklen , Adam R. Talcott , Santosh G. Abraham , Sothea Soun , Sanjay Patel , Farnad Sajjadian
发明人： Lawrence A. Spracklen , Adam R. Talcott , Santosh G. Abraham , Sothea Soun , Sanjay Patel , Farnad Sajjadian
IPC分类号： G06F9/50
CPC分类号： G06F21/71 , G06F12/1027 , G06F2212/683
摘要： In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.
摘要翻译： 在一个实施例中，预期了一种方法。 用户特权线程请求访问硬件加速器。 通过响应请求的较高特权线程向硬件加速器的访问授予用户特权线程。 一个或多个命令由用户特权的线程传送到硬件加速器，而不受较高特权线程的干扰，并响应于授权的访问。 一个或多个命令使硬件加速器执行一个或多个任务。 计算机可读介质包括当各种实施例中被执行时实施该方法的部分的指令，以及硬件加速器和耦合到硬件加速器的处理器。
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10.发明授权Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution 有权在具有推测性执行的无序处理器中提供精确异常的机制公开(公告)号：US06615343B1
公开(公告)日：2003-09-02
申请号：US09599227
申请日：2000-06-22
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3842
摘要： A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set, and based on a class of the exception, processing the exception differently before signaling the trap. The method may include replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception. The method may include replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction. The method may include signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction. The method may include marking an instruction causing the exception as complete without issuing the instruction causing the exception. An apparatus for handling exceptions in a processor includes an instruction scheduler for setting a state upon detection of an exception and signaling a trap for the exception if the state is set. The instruction scheduler, based on a class of the exception, processes the exception differently before signaling the trap.
摘要翻译： 在处理器中处理异常的方法包括在检测到异常时设置状态，如果状态被设置则发信号通知异常的陷阱，并且基于异常类，在发信号通知之前不同地处理异常。 该方法可以包括在基于异常的类发送异常的陷阱之前重放导致异常的指令。 该方法可以包括在导致异常的指令成为最旧的未命令指令之后重放导致异常的指令。 该方法可以包括在导致异常的指令成为最旧的未命令指令之后发信号通知异常的陷阱。 该方法可以包括将导致异常的指令标记为完整，而不发出导致异常的指令。 用于在处理器中处理异常的装置包括指令调度器，用于在检测到异常时设置状态，并且如果状态被设置，则发送异常的陷阱。 指令调度程序基于异常类，在通知陷阱之前处理异常。
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