公开(公告)号：US20110320736A1

公开(公告)日：2011-12-29

申请号：US12822734

申请日：2010-06-24

申请人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F9/30

CPC分类号： G06F9/3834

摘要： A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.

摘要翻译： 一种计算机实现的方法，其包括经由处理器在存储队列中接收多个存储，将获取请求与所述存储队列进行比较，以搜索具有与所述提取请求相同的存储器地址的目标存储器，确定所述目标存储 在同一流水线中的提取请求之前，并且当确定目标存储位于提取请求之前时处理提取请求。

公开(公告)号：US08407442B2

公开(公告)日：2013-03-26

申请号：US12822734

申请日：2010-06-24

申请人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3834

摘要： A computer-program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.

摘要翻译： 一种计算机程序产品，其包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括经由处理器在存储队列中接收多个存储，将获取请求与存储队列进行比较，以搜索具有与获取请求相同的存储器地址的目标存储，确定目标存储是否在 在同一流水线中提取请求，并且当确定目标存储在提取请求之前时处理该提取请求。

公开(公告)号：US20120215995A1

公开(公告)日：2012-08-23

申请号：US13459598

申请日：2012-04-30

申请人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/00

CPC分类号： G06F9/3834

摘要： A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.

摘要翻译： 一种计算机实现的方法，其包括经由处理器在存储队列中接收多个存储，将获取请求与所述存储队列进行比较，以搜索具有与所述提取请求相同的存储器地址的目标存储器，确定所述目标存储 在同一流水线中的提取请求之前，并且当确定目标存储位于提取请求之前时处理提取请求。

公开(公告)号：US08539190B2

公开(公告)日：2013-09-17

申请号：US13459598

申请日：2012-04-30

申请人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter

发明人： Deanna Postles Dunn Berger ,  Michael Fee ,  Robert J. Sonnelitter

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3834

摘要： A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.

摘要翻译： 一种计算机实现的方法，其包括经由处理器在存储队列中接收多个存储，将获取请求与所述存储队列进行比较，以搜索具有与所述提取请求相同的存储器地址的目标存储器，确定所述目标存储 在同一流水线中的提取请求之前，并且当确定目标存储位于提取请求之前时处理提取请求。

公开(公告)号：US20110320721A1

公开(公告)日：2011-12-29

申请号：US12822884

申请日：2010-06-24

申请人： Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0897 ,  G06F2212/1024

摘要： A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is available, bypassing an intervening memory between the higher level memory and the lower level memory when it is determined that the data bus is available, and transferring the requested data directly from the higher level memory to the lower level memory.

摘要翻译： 一种用于管理多级存储器层级中的数据传输的计算机实现的方法，包括：接收用于在较高级存储器中分配数据的提取请求，确定所述较高级存储器和较低级存储器之间的数据总线是否可用， 当确定数据总线可用时，绕过高级存储器和较低级存储器之间的中间存储器，并将所请求的数据直接从较高级存储器传送到下级存储器。

公开(公告)号：US20110320722A1

公开(公告)日：2011-12-29

申请号：US12821744

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Garrett M. Drapala ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Garrett M. Drapala ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F9/30

CPC分类号： G06F12/084 ,  G06F12/0855

摘要： An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first command type, a second subset of the plurality of command queues being assigned to process commands of the second command type, and a third subset of the plurality of the command queues not being assigned to either the first subset or the second subset. The apparatus also includes an input controller configured to receive requests having the first command type and the second command type and assign requests having the first command type to command queues in the first subset until all command queues in the first subset are filled and then assign requests having the first command type to command queues in the third subset.

摘要翻译： 一种用于控制对流水线的访问的装置，包括多个命令队列，包括被分配处理第一命令类型的命令的多个命令队列的第一子集，多个命令队列的第二子集被分配给 第二命令类型，并且多个命令队列的第三子集未被分配给第一子集或第二子集。 该装置还包括输入控制器，其被配置为接收具有第一命令类型和第二命令类型的请求，并且分配具有第一命令类型的请求来命令第一子集中的队列，直到第一子集中的所有命令队列被填满，然后分配请求 具有第一种命令类型来命令第三个子集中的队列。

公开(公告)号：US08635409B2

公开(公告)日：2014-01-21

申请号：US12821706

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0846

摘要： A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a selected request the selected request having been provided by a first state machine; determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache; determining that the location in the cache is unavailable; and replacing the mode with a modified mode that only includes the second step.

摘要翻译： 向缓存流水线提供请求的方法包括：从仲裁器的一个或多个状态机接收多个请求; 从所选择的请求中选择所述多个请求中的一个请求，所述请求已由第一状态机提供; 确定所选择的请求包括需要第一步骤和第二步骤的模式，所述第一步骤包括对高速缓存中的位置的访问; 确定高速缓存中的位置不可用; 并用仅包括第二步的修改模式替换该模式。

公开(公告)号：US08407420B2

公开(公告)日：2013-03-26

申请号：US12821721

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F13/00 ,  G06F12/08

CPC分类号： G06F12/0857 ,  G06F12/084

摘要： A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed. The first requester may be a lower level cache such as an L2 cache, or an I/O device and the second requester may be an upper level cache such as an L4 cache, and the first request may be a coherency request.

摘要翻译： 一种用于在耦合到第一请求者和第二请求者的共享高速缓存中执行操作的存储器系统，装置和方法。 该方法包括在共享缓存中接收来自第二请求者的第一请求; 将请求分配给状态机; 将来自状态机的第一管道通过请求发送到仲裁器; 提供从所述第一管道通过请求到高速缓存流水线的第一指令，所述第一指令引起第一管道通过; 以及在第一管道通过完成之前向仲裁者提供第二管道通过请求。 第一请求者可以是诸如L2高速缓存或I / O设备的低级缓存，并且第二请求者可以是诸如L4高速缓存的上级高速缓存，并且第一请求可以是一致性请求。

公开(公告)号：US09378023B2

公开(公告)日：2016-06-28

申请号：US13495201

申请日：2012-06-13

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski, Jr. ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski, Jr. ,  Diane L. Orf

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F13/16 ,  G06F13/18 ,  G06F9/54 ,  G06F13/14

CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

公开(公告)号：US20130339701A1

公开(公告)日：2013-12-19

申请号：US13495201

申请日：2012-06-13

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski,, JR. ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski,, JR. ,  Diane L. Orf

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

摘要翻译： 实施例涉及用于多管线计算机处理器的跨管道串行化。 一个方面包括由处理器接收处理器，该处理器包括第一流水线，第一流水线包括串行化流水线和第二流水线，第二流水线包括非串行流水线，包括第一流水线的第一子请求的请求和 第二个管道的第二个子请求。 另一方面包括通过第一管道完成第一个子请求。 另一方面包括，基于通过第一管道完成第一子请求，将第一管道的跨管解锁信号发送到第二管道。 另一方面包括，基于通过第二管线接收横管解锁信号，通过第二管道完成第二子请求。