公开(公告)号：US07772124B2

公开(公告)日：2010-08-10

申请号：US12140439

申请日：2008-06-17

申请人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, Jr. ,  Jiansheng Xu

发明人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, Jr. ,  Jiansheng Xu

IPC分类号： H01L21/311

CPC分类号： H01L23/64 ,  H01L23/481 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/19011 ,  H01L2924/19104 ,  H01L2924/00

摘要： A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

摘要翻译： 通过带通滤波器形成通硅的方法包括形成包括硅层的衬底并在硅层的底侧提供金属层。 另外，该方法包括在硅层的顶侧设置电介质层，并且在电介质层的表面上通过带通滤波器形成通硅的顶侧互连。 此外，该方法包括在电介质层中形成与顶侧互连接触的多个触点，并分别通过衬底形成多个穿硅通孔并与多个触点和金属层接触。

公开(公告)号：US20090311841A1

公开(公告)日：2009-12-17

申请号：US12140439

申请日：2008-06-17

申请人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

发明人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

IPC分类号： H01L21/02 ,  H01L21/4763

CPC分类号： H01L23/64 ,  H01L23/481 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/19011 ,  H01L2924/19104 ,  H01L2924/00

摘要： A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

摘要翻译： 通过带通滤波器形成通硅的方法包括形成包括硅层的衬底并在硅层的底侧提供金属层。 另外，该方法包括在硅层的顶侧设置电介质层，并且在电介质层的表面上通过带通滤波器形成通硅的顶侧互连。 此外，该方法包括在电介质层中形成与顶侧互连接触的多个触点，并分别通过衬底形成多个穿硅通孔并与多个触点和金属层接触。

公开(公告)号：US20090309675A1

公开(公告)日：2009-12-17

申请号：US12140364

申请日：2008-06-17

申请人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

发明人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

IPC分类号： H03H7/00

CPC分类号： H01P1/20363

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silicon layer and a dielectric layer on a top side of the silicon layer. Additionally, the design structure includes a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer and a plurality of contacts in the dielectric layer in contact with the top-side interconnect. Further, the design structure includes a plurality of through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括具有硅层的基板。 此外，设计结构包括在硅层的底侧上的金属层和在硅层的顶侧上的介电层。 此外，该设计结构包括在电介质层的表面上的通过硅通孔带通滤波器的顶侧互连以及与顶侧互连件接触的介电层中的多个触点。 此外，设计结构包括分别通过基板并与多个触点和金属层接触的多个穿硅通孔。

公开(公告)号：US20120193121A1

公开(公告)日：2012-08-02

申请号：US13018963

申请日：2011-02-01

申请人： Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, JR.

发明人： Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, JR.

IPC分类号： H01B9/02 ,  H01B13/016 ,  G06F17/50

CPC分类号： H01L21/768 ,  G06F17/505 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49123 ,  H01L2924/00

摘要： A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

摘要翻译： 提供了一种高性能的片上垂直同轴电缆结构，其制造方法和设计结构。 同轴电缆结构包括同轴地围绕内导体的内导体和绝缘材料。 该结构还包括围绕绝缘材料的外导体。 内导体和外导体都包括形成在不同布线层上的多个金属层，并且通过导体在不同布线层之间互连。 同轴电缆结构形成在半导体衬底的表面上并且与表面基本上垂直对齐。

公开(公告)号：US08413098B2

公开(公告)日：2013-04-02

申请号：US12431887

申请日：2009-04-29

申请人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, Jr.

发明人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, Jr.

IPC分类号： G06F17/50

CPC分类号： H01L23/5225 ,  G06F17/5036 ,  G06F17/5063 ,  G06F17/5072 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.

摘要翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模。 T形连接件包括一个导电T形接头，它包括主体和从本体的相互垂直的侧面突出的第一，第二和第三整体臂，三个整体臂的每个臂具有与主体相邻的相同的第一宽度和相同的长度 远离身体; 导电性阶梯结，其包括具有第一宽度的第一部分和具有第二宽度的整体和邻接的第二部分，所述第二宽度不同于所述第一宽度，所述第一部分平滑地抵接并与所述第二部分 交界处 并且其中T形结和台阶结的顶表面是共面的。

公开(公告)号：US20100156559A1

公开(公告)日：2010-06-24

申请号：US12342271

申请日：2008-12-23

申请人： Guoan Wang ,  Essam Mina

发明人： Guoan Wang ,  Essam Mina

IPC分类号： H01P1/18 ,  H01P3/08 ,  G06F19/00

CPC分类号： H01P3/026 ,  H01P1/184 ,  H01P3/088

摘要： A grounding plate and a transmission line are provided in a stack of dielectric material layers. First transmission line portions having a first width are alternately interlaced with second transmission line portions having a second width in the transmission line. The second width is greater than the first width so that inductance of the transmission line is increased relative to a transmission line having a fixed width. Metal fins may be provided between the grounding plate and the transmission line in the stack of the dielectric material layers. The metal fins may be grounded to the grounding plate to increase capacitance between the transmission line and the grounding plate. The increase in the inductance and the capacitance per unit length between the transmission line and the grounding plate is advantageously employed to provide a reduced phase velocity for electromagnetic signal transmitted through the transmission line. A design structure for the transmission line structure is provided.

摘要翻译： 接地板和传输线设置在电介质材料层的堆叠中。 具有第一宽度的第一传输线部分与传输线中具有第二宽度的第二传输线部分交替交织。 第二宽度大于第一宽度，使得传输线的电感相对于具有固定宽度的传输线增加。 可以在接地板和介电材料层的叠层中的传输线之间设置金属翅片。 金属翅片可以接地到接地板，以增加传输线和接地板之间的电容。 传输线和接地板之间的电感和每单位长度的电容的增加有利地用于为通过传输线传输的电磁信号提供降低的相位速度。 提供了传输线结构的设计结构。

公开(公告)号：US08640076B2

公开(公告)日：2014-01-28

申请号：US12906707

申请日：2010-10-18

申请人： Essam Mina ,  Guoan Wang

发明人： Essam Mina ,  Guoan Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

摘要翻译： 提供了开发金属填充作为库装置的方法，特别是在集成电路和设计结构中产生金属填充物的效应（例如电容）的模型的方法。 该方法在计算设备上实现，并且包括生成用于集成电路中的金属填充效应的模型。 金属填充模型在完成集成电路的布局设计之前生成。

公开(公告)号：US08212634B2

公开(公告)日：2012-07-03

申请号：US12478385

申请日：2009-06-04

申请人： Essam Mina ,  Guoan Wang

发明人： Essam Mina ,  Guoan Wang

IPC分类号： H01P3/00 ,  H01P3/18

CPC分类号： H01P3/003 ,  H01P3/085

摘要： An on-chip vertical coplanar waveguide with tunable characteristic impedance, a design structure, and a method of making the same. An on-chip transmission line includes a signal line, an upper ground line spaced apart from and above the signal line, and a lower ground line spaced apart from and below the signal line. The signal line, the upper ground line and the lower ground line are substantially vertically aligned in a dielectric material.

摘要翻译： 具有可调谐特性阻抗的片上垂直共面波导，设计结构及其制造方法。 片上传输线包括信号线，与信号线间隔开的上接地线以及与信号线间隔开的下接地线。 信号线，上地线和下接地线在电介质材料中基本垂直对准。

公开(公告)号：US08766747B2

公开(公告)日：2014-07-01

申请号：US12752554

申请日：2010-04-01

申请人： Essam Mina ,  Guoan Wang

发明人： Essam Mina ,  Guoan Wang

IPC分类号： H01P3/08 ,  H01P9/00

CPC分类号： H01P3/081 ,  H01P3/003 ,  H01P9/00

摘要： On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion. The wide portion extends toward the at least one ground.

摘要翻译： 本文提供片上高性能慢波共面波导结构，集成电路的制造方法和设计结构。 该结构包括设置在与至少一个地面相同的平面中的至少一个地面和信号层。 信号层具有至少一个交替宽的部分和窄部分。 宽部分朝向至少一个地面延伸。

公开(公告)号：US08629536B2

公开(公告)日：2014-01-14

申请号：US13018963

申请日：2011-02-01

申请人： Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, Jr.

发明人： Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, Jr.

IPC分类号： H01L29/40

CPC分类号： H01L21/768 ,  G06F17/505 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49123 ,  H01L2924/00

摘要： A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

摘要翻译： 提供了一种高性能的片上垂直同轴电缆结构，其制造方法和设计结构。 同轴电缆结构包括同轴地围绕内导体的内导体和绝缘材料。 该结构还包括围绕绝缘材料的外导体。 内导体和外导体都包括形成在不同布线层上的多个金属层，并且通过导体在不同布线层之间互连。 同轴电缆结构形成在半导体衬底的表面上并且与表面基本上垂直对齐。