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    Structure for a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter
    2.
    发明申请
    Structure for a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter 有权
    通过硅片通过片上无源MMW带通滤波器的结构

    公开(公告)号：US20090309675A1

    公开(公告)日：2009-12-17

    申请号：US12140364

    申请日：2008-06-17

    申请人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

    发明人： Amit Bavisi ,  Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

    IPC分类号： H03H7/00

    CPC分类号： H01P1/20363

    摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silicon layer and a dielectric layer on a top side of the silicon layer. Additionally, the design structure includes a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer and a plurality of contacts in the dielectric layer in contact with the top-side interconnect. Further, the design structure includes a plurality of through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

    摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括具有硅层的基板。 此外，设计结构包括在硅层的底侧上的金属层和在硅层的顶侧上的介电层。 此外，该设计结构包括在电介质层的表面上的通过硅通孔带通滤波器的顶侧互连以及与顶侧互连件接触的介电层中的多个触点。 此外，设计结构包括分别通过基板并与多个触点和金属层接触的多个穿硅通孔。

    MILLIMETER-WAVE ON-CHIP SWITCH EMPLOYING FREQUENCY-DEPENDENT INDUCTANCE FOR CANCELLATION OF OFF-STATE CAPACITANCE
    3.
    发明申请
    MILLIMETER-WAVE ON-CHIP SWITCH EMPLOYING FREQUENCY-DEPENDENT INDUCTANCE FOR CANCELLATION OF OFF-STATE CAPACITANCE 有权
    采用离散电源的毫米波片式开关，用于取消非状态电容的频率依赖性电感

    公开(公告)号：US20120019313A1

    公开(公告)日：2012-01-26

    申请号：US12839777

    申请日：2010-07-20

    申请人： Wayne H. Woods, JR. ,  Guoan Wang ,  Hanyi Ding

    发明人： Wayne H. Woods, JR. ,  Guoan Wang ,  Hanyi Ding

    IPC分类号： H01P1/20

    CPC分类号： H01P1/127 ,  H01F17/0006 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L27/0629 ,  H01L28/10 ,  H01L2223/6627 ,  H01L2924/0002 ,  H03K17/145 ,  H01L2924/00

    摘要： A semiconductor switching device includes a field effect transistor and an inductor structure that provides a frequency dependent inductance in a parallel connection. During the off-state of the semiconductor switching device, the frequency dependent impedance component due to the off-state parasitic capacitance of the switching device is cancelled by the frequency dependent inductance component of the inductor structure, which provides a non-linear impedance as a function of frequency. The inductor structure provides less inductance at a higher operating frequency than at a lower operating frequency to provide more effective cancellation of two impedance components of the parasitic capacitance and the inductance. Thus, the semiconductor switching device can provide low parasitic coupling at multiple operating frequencies. The operating frequencies of the semiconductor switching device can be at gigahertz ranges for millimeter wave applications.

    摘要翻译： 半导体开关器件包括场效应晶体管和在并联连接中提供频率相关电感的电感器结构。 在半导体开关器件的截止状态期间，由开关器件的截止状态寄生电容引起的与频率相关的阻抗分量被电感器结构的频率相关的电感分量抵消，该电感器结构提供非线性阻抗作为 频率功能 电感器结构在较高工作频率下提供比在较低工作频率下更小的电感，以提供更有效地消除寄生电容和电感的两个阻抗分量。 因此，半导体开关器件可以在多个工作频率下提供低的寄生耦合。 对于毫米波应用，半导体开关器件的工作频率可以是千兆赫兹范围。

    Compact On-Chip Branchline Coupler Using Slow Wave Transmission Line
    4.
    发明申请
    Compact On-Chip Branchline Coupler Using Slow Wave Transmission Line 有权
    使用慢波传输线的紧凑型片上分支线耦合器

    公开(公告)号：US20110043299A1

    公开(公告)日：2011-02-24

    申请号：US12542958

    申请日：2009-08-18

    申请人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, JR.

    发明人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, JR.

    IPC分类号： H01P5/18 ,  H01P1/18

    CPC分类号： H01P3/082 ,  H01L27/0617 ,  H01L27/0629 ,  H01P5/227

    摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

    摘要翻译： 使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。 支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。 高阻抗和低阻抗是相对的。 高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。 宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。

    ON-CHIP RADIAL CAVITY POWER DIVIDER/COMBINER
    6.
    发明申请
    ON-CHIP RADIAL CAVITY POWER DIVIDER/COMBINER 有权
    片上径向辐射功率分配器/组合器

    公开(公告)号：US20130193584A1

    公开(公告)日：2013-08-01

    申请号：US13358792

    申请日：2012-01-26

    申请人： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, JR.

    发明人： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, JR.

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/481 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

    摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

    摘要翻译： 公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。 分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。 互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。 每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。 对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。 对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

    SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE
    7.
    发明申请
    SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE 有权
    用于片上电容开机终止的芯片建模解决方案

    公开(公告)号：US20120317530A1

    公开(公告)日：2012-12-13

    申请号：US13158562

    申请日：2011-06-13

    申请人： Michael P. Keene ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

    发明人： Michael P. Keene ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5081

    摘要： A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design.

    摘要翻译： 公开了一种用于生成用于集成电路设计的库对象的计算机实现的方法。 在一个实施例中，该方法包括：分析一对集成电路设计对象，用于一对集成电路设计对象之间的边缘电容效应; 并在完成集成电路设计的布局设计之前生成考虑到边缘电容效应的库对象。

    Design Structure, Structure and Method for Providing an On-Chip Variable Delay Transmission Line With Fixed Characteristic Impedance
    8.
    发明申请
    Design Structure, Structure and Method for Providing an On-Chip Variable Delay Transmission Line With Fixed Characteristic Impedance 有权
    提供具有固定特性阻抗的片上可变延迟传输线的设计结构，结构和方法

    公开(公告)号：US20090315641A1

    公开(公告)日：2009-12-24

    申请号：US12144684

    申请日：2008-06-24

    申请人： Hanyi Ding ,  Wayne H. Woods, JR.

    发明人： Hanyi Ding ,  Wayne H. Woods, JR.

    IPC分类号： H01P1/18

    CPC分类号： H01P9/00 ,  H01P1/184

    摘要： A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

    摘要翻译： 一种用于提供具有固定特性阻抗的片上可变延迟传输线的设计结构，结构和方法。 制造传输线结构的方法包括形成传输线结构的信号线，形成在传输线结构中引起第一延迟和第一特性阻抗的第一接地返回结构，以及形成第二接地返回结构，其导致 传输线结构中的第二延迟和第二特性阻抗。 第一延迟与第二延迟不同，第一特征阻抗基本上与第二特征阻抗相同。

    Chip Inductor With Frequency Dependent Inductance
    9.
    发明申请
    Chip Inductor With Frequency Dependent Inductance 有权
    具有频率依赖电感的片式电感器

    公开(公告)号：US20100237464A1

    公开(公告)日：2010-09-23

    申请号：US12632030

    申请日：2009-12-07

    申请人： Hanyi Ding ,  Wayne H. Woods, JR.

    发明人： Hanyi Ding ,  Wayne H. Woods, JR.

    IPC分类号： H01L27/06 ,  G06F17/50

    CPC分类号： H01L28/10 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/31053 ,  H01L21/76808 ,  H01L21/76826 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L29/432 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

    摘要翻译： 包括信号传输金属线和电容接地感应信号耦合金属线的一组金属线结构被嵌入在电介质材料层中。 电容器串联连接在电容接地的感应信号耦合金属线路和可能在输入侧或输出侧的局部电接地之间。 金属线结构和电容集合提供了一个频率相关的电感。 频率依赖电感器的Q因子具有多个峰值，使得能够在多个频率下操作频率相关的电感器。 可以在频率相关电感器中提供多个电容耦合的感应信号耦合金属线路，每个电路通过电容器连接到本地电接地。 通过选择电容器的不同电容值，可以在不同信号频率的频率相关电感器中获得Q因子的多个值。