公开(公告)号：US20200243761A1

公开(公告)日：2020-07-30

申请号：US16845405

申请日：2020-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Kerry Joseph NAGEL ,  Chaitanya MUDIVARTHI ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US20190334082A1

公开(公告)日：2019-10-31

申请号：US16508450

申请日：2019-07-11

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Kerry Joseph NAGEL

IPC: H01L43/12 ,  G11B5/84 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.

公开(公告)号：US20190067566A1

公开(公告)日：2019-02-28

申请号：US16108762

申请日：2018-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Sarin A. DESHPANDE

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

公开(公告)号：US20180375018A1

公开(公告)日：2018-12-27

申请号：US16050749

申请日：2018-07-31

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Kerry Joseph NAGEL ,  Chaitanya MUDIVARTHI ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US20180309051A1

公开(公告)日：2018-10-25

申请号：US15958444

申请日：2018-04-20

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Moazzem HOSSAIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L21/022 ,  H01L21/02203 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.