公开(公告)号：US12119220B2

公开(公告)日：2024-10-15

申请号：US18079160

申请日：2022-12-12

Applicant: ASM IP Holding B.V.

Inventor： Leo Salmi ,  Mikko Ritala ,  Markku Leskelä

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02203 ,  H01L21/02227 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02205

Abstract: A method for filling a gap feature on a substrate surface is disclosed. The method may include: providing a substrate comprising a non-planar surface including one or more gap features; depositing a metal oxide film over a surface of the one or more gap features by a cyclical deposition process; contacting the metal oxide with an organic ligand vapor; and converting at least a portion of the metal oxide film to a porous material thereby filling the one or more gap features. Semiconductor structures including a metal-organic framework material formed by the methods of the disclosure are also disclosed.

公开(公告)号：US20240322011A1

公开(公告)日：2024-09-26

申请号：US18737803

申请日：2024-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Yi PENG ,  Wen-Yuan CHEN ,  Wen-Hsing HSIEH ,  Yi-Ju HSU ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

公开(公告)号：US20230260781A1

公开(公告)日：2023-08-17

申请号：US18305639

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/02203 ,  H01L23/5329 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/02362 ,  H01L29/0649

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US20230223270A1

公开(公告)日：2023-07-13

申请号：US17997155

申请日：2021-04-15

Applicant: Tokyo Electron Limited

Inventor： Takehiko ORII ,  Nobuhiro TAKAHASHI

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/67069 ,  H01L21/02203 ,  H01L21/31116

Abstract: An etching method of supplying etching gases to a substrate to etch a surface of the substrate, includes a protection step of supplying amine gas to the substrate having an oxygen-containing silicon film to form a protective film for preventing etching by the etching gases on a surface of the oxygen-containing silicon film, for protecting the oxygen-containing silicon film, and a first etching step of supplying a first etching gas, which is one of the etching gases and is a fluorine-containing gas, and the amine gas to the substrate to etch the oxygen-containing silicon film.

公开(公告)号：US20230170207A1

公开(公告)日：2023-06-01

申请号：US18079160

申请日：2022-12-12

Applicant: ASM IP Holding B.V.

Inventor： Leo Salmi ,  Mikko Ritala ,  Markku Leskelä

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02203 ,  H01L21/76224 ,  H01L21/0228 ,  H01L21/02227 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02178

Abstract: A method for filling a gap feature on a substrate surface is disclosed. The method may include: providing a substrate comprising a non-planar surface including one or more gap features; depositing a metal oxide film over a surface of the one or more gap features by a cyclical deposition process; contacting the metal oxide with an organic ligand vapor; and converting at least a portion of the metal oxide film to a porous material thereby filling the one or more gap features. Semiconductor structures including a metal-organic framework material formed by the methods of the disclosure are also disclosed.

公开(公告)号：US20180309051A1

公开(公告)日：2018-10-25

申请号：US15958444

申请日：2018-04-20

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Moazzem HOSSAIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L21/022 ,  H01L21/02203 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.

公开(公告)号：US20180226293A1

公开(公告)日：2018-08-09

申请号：US15942947

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

公开(公告)号：US20180138034A1

公开(公告)日：2018-05-17

申请号：US15352118

申请日：2016-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Yen LIN ,  Ching-Yu CHANG ,  Kuei-Shun CHEN ,  Chin-Hsiang LIN

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/09 ,  G03F7/004 ,  G03F7/16 ,  G03F7/038 ,  G03F7/20 ,  G03F7/32

CPC classification number: H01L21/0273 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/0382 ,  G03F7/091 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/322 ,  G03F7/325 ,  H01L21/02203 ,  H01L21/0332 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.

公开(公告)号：US20180122630A1

公开(公告)日：2018-05-03

申请号：US15360016

申请日：2016-11-23

Applicant: Applied Materials, Inc.

Inventor： Kurtis S. Leschkies ,  Keith Tatseun Wong ,  Steven Verhaverbeke

IPC: H01L21/02

CPC classification number: H01L21/02203 ,  H01L21/02337

Abstract: Methods are described for reducing the wet etch rate of dielectric films formed on a patterned substrate by flowing the material into gaps during deposition. Films deposited in this manner may initially exhibit elevated wet etch rates. The dielectric films are treated by exposing the patterned substrate to a high pressure of water vapor in the gas phase. The treatment may reduce the wet etch rate of the dielectric films, especially the gapfill portion of the dielectric film. Scanning electron microscopy has confirmed that the quantity and/or size of pores is reduced or eliminated by the procedures described herein. The treatment has also been found to reduce the etch rate, e.g., at the bottom of gaps filled with the dielectric film.

公开(公告)号：US09941157B2

公开(公告)日：2018-04-10

申请号：US14752097

申请日：2015-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/31 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.