公开(公告)号：US20190103555A1

公开(公告)日：2019-04-04

申请号：US16194523

申请日：2018-11-19

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Kenneth H. SMITH ,  Moazzem HOSSAIN ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L21/3213 ,  H01L21/768 ,  H01L43/08 ,  H01L43/02 ,  H01L21/285 ,  H01L27/22

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US20190237665A1

公开(公告)日：2019-08-01

申请号：US16380589

申请日：2019-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Moazzem HOSSAIN

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  G11C11/16 ,  H01L43/02

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.

公开(公告)号：US20230225217A1

公开(公告)日：2023-07-13

申请号：US18185003

申请日：2023-03-16

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Kenneth SMITH ,  Moazzem HOSSAIN ,  Sanjeev AGGARWAL

IPC: H10B61/00

CPC classification number: H10B61/10

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US20210280778A1

公开(公告)日：2021-09-09

申请号：US17317061

申请日：2021-05-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Kenneth SMITH ,  Moazzem HOSSAIN ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L43/02

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US20180309051A1

公开(公告)日：2018-10-25

申请号：US15958444

申请日：2018-04-20

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Moazzem HOSSAIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L21/022 ,  H01L21/02203 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.