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78 条记录 (耗时 0.026 秒)

    Optical trigger for PICA technique
    23.
    发明申请
    Optical trigger for PICA technique 失效
    PICA技术的光触发器

    公开(公告)号：US20060220664A1

    公开(公告)日：2006-10-05

    申请号：US11098850

    申请日：2005-04-05

    申请人： Franco Stellari ,  Peilin Song

    发明人： Franco Stellari ,  Peilin Song

    IPC分类号： G01R31/302

    CPC分类号： G01R31/31709 ,  G01R31/311

    摘要： Optical triggering system and method for synchronizing a test of an integrated circuit chip with its operation. An optical triggering system includes a testing mechanism, such as a PICA testing mechanism, for testing an integrated circuit chip. An optical trigger mechanism generates an optical trigger signal for synchronizing a test of the integrated circuit chip with its operation. The optical trigger mechanism provides an optical trigger signal having reduced jitter and a higher frequency rate than an electrical trigger signal resulting in a more accurate test of the integrated circuit chip.

    摘要翻译： 用于使集成电路芯片的测试与其操作同步的光触发系统和方法。 光触发系统包括用于测试集成电路芯片的诸如PICA测试机构的测试机构。 光学触发机构产生用于使集成电路芯片的测试与其操作同步的光学触发信号。 光学触发机构提供具有比电触发信号更少的抖动和更高频率的光学触发信号，导致集成电路芯片的更准确的测试。

    On-chip power supply noise detector
    24.
    发明申请
    On-chip power supply noise detector 失效
    片上电源噪声检测器

    公开(公告)号：US20060214672A1

    公开(公告)日：2006-09-28

    申请号：US11089215

    申请日：2005-03-24

    申请人： Keith Jenkins ,  Anuja Sehgal ,  Peilin Song

    发明人： Keith Jenkins ,  Anuja Sehgal ,  Peilin Song

    IPC分类号： G01R27/08

    CPC分类号： G01R31/3004 ,  G01R19/16552

    摘要： Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit comprises the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning comprises shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison comprises detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.

    摘要翻译： 公开了片上检测集成电路电源噪声的技术。 作为示例，用于监视集成电路中的电源线的技术包括以下步骤/操作。 第一信号和第二信号被预处理。 第一信号代表被监测的电源线的电压。 第二信号代表参考电源线的电压。 预处理包括使电压的各个电平移动，使得电压在比较器电路的输入电压范围内。 然后，根据比较器电路对预处理的第一信号和预处理的第二信号进行比较。 比较包括检测预处理的第一信号的电压电平与预处理的第二信号的电压电平之间的差异。

    Method and apparatus for improving transition fault testability of semiconductor chips
    25.
    发明授权
    Method and apparatus for improving transition fault testability of semiconductor chips 失效
    改善半导体芯片的过渡故障可测性的方法和装置

    公开(公告)号：US06453436B1

    公开(公告)日：2002-09-17

    申请号：US09473811

    申请日：1999-12-28

    申请人： Richard F. Rizzolo ,  Peilin Song

    发明人： Richard F. Rizzolo ,  Peilin Song

    IPC分类号： G01R3128

    CPC分类号： G01R31/318525 ,  G01R31/31853 ,  G01R31/31858

    摘要： A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch, a second shift register latch, and a third shift register latch. A first multiplexor is connected between the first and second shift register latches, and a second multiplexor is connected between the second and third shift register latches. Each multiplexor is configured for implementing a jump mode such that a logic value may be passed via the first multiplexor from the first shift register latch to the third shift register latch.

    摘要翻译： 提供扫描链锁存电路。 扫描链锁存电路包括第一移位寄存器锁存器，第二移位寄存器锁存器和第三移位寄存器锁存器。 第一复用器连接在第一和第二移位寄存器锁存器之间，第二多路复用器连接在第二和第三移位寄存器锁存器之间。 每个多路复用器被配置为实现跳跃模式，使得逻辑值可以经由第一多路复用器从第一移位寄存器锁存器传递到第三移位寄存器锁存器。

    System and method for virtual control of laboratory equipment
    26.
    发明授权
    System and method for virtual control of laboratory equipment 失效
    实验室设备虚拟控制系统及方法

    公开(公告)号：US08041437B2

    公开(公告)日：2011-10-18

    申请号：US12103554

    申请日：2008-04-15

    申请人： Franco Stellari ,  Steven E. Steen ,  Peilin Song

    发明人： Franco Stellari ,  Steven E. Steen ,  Peilin Song

    IPC分类号： G05B19/18

    CPC分类号： G05B15/02 ,  G06F19/00

    摘要： A system for virtual control of electronic laboratory equipment includes a local computer system. One or more items of electronic laboratory equipment are connected to the local computer system. Each item of electronic laboratory equipment has a physical control panel including one or more displays or controls. A virtual control panel generation unit generates a virtual control panel accessible from a remote computer system. The virtual control panel is substantially similar to the physical control panel in appearance. A command interpretation unit monitors interaction between the remote user and the virtual control panel and generates electronic laboratory equipment commands for exploiting the functionality of the electronic laboratory equipment.

    摘要翻译： 用于虚拟控制电子实验室设备的系统包括本地计算机系统。 一台或多台电子实验室设备连接到本地计算机系统。 电子实验室设备的每个项目都有一个包括一个或多个显示器或控件的物理控制面板。 虚拟控制面板生成单元生成可从远程计算机系统访问的虚拟控制面板。 虚拟控制面板在外观上基本类似于物理控制面板。 命令解释单元监视远程用户和虚拟控制面板之间的交互，并产生用于利用电子实验室设备的功能的电子实验室设备命令。

    ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS
    27.
    发明申请
    ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS 失效
    用于电路分析的固体显微镜中的角度光谱定标

    公开(公告)号：US20110037973A1

    公开(公告)日：2011-02-17

    申请号：US12911781

    申请日：2010-10-26

    申请人： Stephen Bradley Ippolito ,  Darrell L. Miles ,  Peilin Song ,  John D. Sylvestri

    发明人： Stephen Bradley Ippolito ,  Darrell L. Miles ,  Peilin Song ,  John D. Sylvestri

    IPC分类号： G01N21/88

    CPC分类号： G01R31/311

    摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.

    摘要翻译： 用于定位半导体芯片中的故障的结构。 芯片包括电介质互连上的衬底。 包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。 衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。 芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。 如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

    ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES
    28.
    发明申请
    ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES 有权
    电源漏电检测

    公开(公告)号：US20100109700A1

    公开(公告)日：2010-05-06

    申请号：US12684142

    申请日：2010-01-08

    申请人： Frank D. Ferraiolo ,  Anuja Sehgal ,  Peilin Song ,  Michael A. Sperling

    发明人： Frank D. Ferraiolo ,  Anuja Sehgal ,  Peilin Song ,  Michael A. Sperling

    IPC分类号： G01R31/36

    CPC分类号： G01R31/30 ,  G01R31/2884 ,  G01R31/3016 ,  G01R31/31721

    摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

    摘要翻译： 片上传感器检测电源漏洞。 片内传感器采用敏感延迟链和不敏感延迟链，以检测电源下冲和过冲，而无需外部片外部件。 检测到用户定义的阈值之外的下冲和超调。 下冲和过冲由两个延迟链的相位相对差异表示。 两个延迟链可编程，以检测各种频率。

    Constructing Variability Maps by Correlating Off-State Leakage Emission Images to Layout Information
    29.
    发明申请
    Constructing Variability Maps by Correlating Off-State Leakage Emission Images to Layout Information 失效
    通过将非状态泄漏图像关联到布局信息来构建变异图

    公开(公告)号：US20100080445A1

    公开(公告)日：2010-04-01

    申请号：US12241926

    申请日：2008-09-30

    申请人： Stanislav Polonsky ,  Peilin Song ,  Franco Stellari ,  Alan J. Weger

    发明人： Stanislav Polonsky ,  Peilin Song ,  Franco Stellari ,  Alan J. Weger

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.

    摘要翻译： 公开了用于监测或感测集成电路设计中的工艺变化的改进的技术。 这样的技术通过构建将泄漏发射图像与布局信息相关联的可变性图来提供这样的改进。 作为示例，用于监测与被测器件（例如，集成电路）相关联的一个或多个制造工艺变化的方法包括以下步骤。 获得表示与被测设备的泄漏电流相关联的能量发射的发射图像。 发射图像与待测器件的布局相关，以形成交叉发射图像。 选择交叉发射图像上的共同结构并将其识别为感兴趣的区域。 基于与感兴趣区域相关联的能量排放来计算一个或多个可变性度量（例如，品质因素）。 基于所计算的变异性度量创建变异性图，其中可变性图可用于监测与被测设备相关联的一个或多个制造过程变化。

    Process variation on-chip sensor
    30.
    发明申请
    Process variation on-chip sensor 失效
    过程变化片上传感器

    公开(公告)号：US20090206821A1

    公开(公告)日：2009-08-20

    申请号：US12032100

    申请日：2008-02-15

    申请人： Mesut Meterelliyoz ,  Peilin Song ,  Franco Stellari

    发明人： Mesut Meterelliyoz ,  Peilin Song ,  Franco Stellari

    IPC分类号： G01R19/00

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Improved process variation sensors and techniques are disclosed, wherein both global and local variations associated with transistors on an integrated circuit can be monitored. For example, respective circuits for sensing a global process variation, a local process variation between neighboring negative-channel type transistors, and a local process variation between neighboring positive-channel type transistors are disclosed. Further, in one example, a method for sensing a process variation associated with transistors on an integrated circuit includes providing at least one process variation sensor on the integrated circuit, the process variation sensor comprising a sensing portion including one or more transistors and a loading and amplification portion including one or more transistors, and operating the one or more transistors of the sensing portion and the one or more transistors of the loading and amplification portion in a subthreshold region of transistor operation such that when a threshold voltage of at least one of the transistors changes, a process variation is sensed.

    摘要翻译： 公开了改进的工艺变化传感器和技术，其中可以监测与集成电路上的晶体管相关联的全局和局部变化。 例如，公开了用于感测全局处理变化的相应电路，相邻负信道型晶体管之间的局部处理变化以及相邻正通道型晶体管之间的局部工艺变化。 此外，在一个示例中，用于感测与集成电路上的晶体管相关联的工艺变化的方法包括在集成电路上提供至少一个工艺变化传感器，所述工艺变化传感器包括感测部分，其包括一个或多个晶体管， 放大部分包括一个或多个晶体管，并且在晶体管操作的亚阈值区域中操作感测部分的一个或多个晶体管和负载和放大部分的一个或多个晶体管，使得当晶体管操作中的至少一个的阈值电压 晶体管变化，感测到工艺变化。