公开(公告)号：US07741877B2

公开(公告)日：2010-06-22

申请号：US11713469

申请日：2007-03-01

Applicant: Philippe Roche ,  Francois Jacquet ,  Jean-Jacques De Jong

Inventor： Philippe Roche ,  Francois Jacquet ,  Jean-Jacques De Jong

IPC: H03K19/00 ,  G06F1/04

CPC classification number: H03K19/00338 ,  G06F1/10 ,  G06F1/24 ,  H03K5/1506

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract translation: 本发明的一个实施例涉及一种用于分发初始信号的电路，包括接收初始信号的输入节点，每个向电路组件提供至少一个结果信号的多个终端节点，以及输入节点和 连接多个中间节点的多个终端节点，其中连接分支被复制，使得输入节点和中间节点之间的每个节点包括两个输入和两个输出，允许初始信号向终端双重传播 节点通过重复连接分支，每个终端节点终端节点接收两个输入信号，初始信号的图像并提供所得到的初始信号：如果所述输入信号相同或不活动，则输入信号的图像如果输入信号不同 从彼此。

公开(公告)号：US07623400B2

公开(公告)日：2009-11-24

申请号：US11824948

申请日：2007-07-03

Applicant: Francois Jacquet ,  Franck Genevaux

Inventor： Francois Jacquet ,  Franck Genevaux

IPC: G11C7/02

CPC classification number: G11C7/14 ,  G11C7/08

Abstract: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

Abstract translation: 本发明的实施例涉及包括由位于行和列的交点处的存储器单元组成的存储器平面的存储器件，以及设计成输出信号以激活布置在存储器中的列的底部的读取放大器的虚拟路径 所述虚拟路径包括连接在两个虚拟位线之间的虚拟存储器单元，所述虚拟存储单元选择至少一个设计成对所述虚拟位线中的至少一个排放的虚拟单元，以及连接到所述两个虚拟位线的控制单元以产生所述激活信号 其特征在于，所述设备包括对所选择的单元的数量进行编程以便至少对所述虚拟位线进行排放的装置，以调整所述激活信号输出的时间。

公开(公告)号：US07327594B2

公开(公告)日：2008-02-05

申请号：US11433046

申请日：2006-05-12

Applicant: Francois Jacquet

Inventor： Francois Jacquet

IPC: G11C17/00 ,  G11C5/02

CPC classification number: G11C17/00 ,  G11C7/18

Abstract: Bit lines (BL0, BL0R, BL1, BL1R, . . . ) of a ROM memory array with differential detection reading are arranged within two overlaid metallization levels so as to increase the read reliability of binary values stored in the array. The ROM array is divided into matrix segments (100, 101, . . . ) aligned parallel to the bit lines. The bit lines are shifted horizontally and/or vertically within transition regions (T) located between the segments of matrix, by effecting circular permutations between the positions of the bit lines that are divided up into groups of four.

Abstract translation: 具有差分检测读取的ROM存储器阵列的位线（BL 0，BL 0 R，BL 1，BL 1 R，...）被布置在两个重叠的金属化电平内，以便增加存储在 数组。 ROM阵列被分成与位线平行排列的矩阵段（100,101 ......）。 位线在位于矩阵的段之间的过渡区域（T）内水平和/或垂直移位，通过在被划分成四组的位线之间进行圆形排列。

公开(公告)号：US07233512B2

公开(公告)日：2007-06-19

申请号：US11048224

申请日：2005-02-01

Applicant: Mark Lysinger ,  Francois Jacquet ,  Phillippe Roche

Inventor： Mark Lysinger ,  Francois Jacquet ,  Phillippe Roche

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.

Abstract translation: 内容可寻址存储器（CAM）电路包括优选地形成为具有内部节点的两个存储器单元的存储器单元。 比较电路与存储器单元一起工作。 存储单元存在公共端（VPL）。 在每个存储单元的内部节点和公共端子之间添加电容器用于存储器单元的稳定性。

公开(公告)号：US07202518B2

公开(公告)日：2007-04-10

申请号：US10877755

申请日：2004-06-25

Applicant: Francois Jacquet ,  Philippe Candellier ,  Robin Cerutti ,  Philippe Coronel ,  Pascale Mazoyer

Inventor： Francois Jacquet ,  Philippe Candellier ,  Robin Cerutti ,  Philippe Coronel ,  Pascale Mazoyer

IPC: H01L27/108

CPC classification number: H01L27/0688 ,  G11C11/405 ,  H01L27/108

Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.

Abstract translation: 集成的动态随机存取存储器元件包括两个用于存储两个相应位的单元。 包括源区和漏区。 每个单元包括具有栅极和在源极和漏极区域之间延伸的中间部分的场效应晶体管。 在每个单元的晶体管的中间部分设置有沟道。 偏振电极被放置在两个晶体管的各个中间部分之间。 该极化电极电容耦合到每个晶体管的中间部分，并用于存储第一和第二位。

公开(公告)号：US20070064467A1

公开(公告)日：2007-03-22

申请号：US11481576

申请日：2006-07-05

Applicant: Francois Jacquet

Inventor： Francois Jacquet

IPC: G11C17/00

CPC classification number: H01L27/112 ,  G11C7/18 ,  G11C17/12

Abstract: An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one, the array comprising a repetition of an elementary pattern extending over three lines in each direction and comprising nine transistors arranged so that each of the lines of the elementary pattern comprises two cells, two neighboring transistors of each pattern in the first direction sharing a same second region connected to a ground line and being connected to different bit lines from a word line to the other.

Abstract translation: 一种ROM单元阵列，每个由具有第一漏极或源极区域的晶体管形成，该第一漏极或源极区域连接到在第一方向上连接多个晶体管的位线，不同晶体管的栅极沿垂直于第一方向的第二方向连接到字线 一个，该阵列包括在每个方向上三条线上延伸的基本图案的重复，并且包括九个晶体管，其布置成使得基本图案的每条线包括两个单元，在第一方向上的每个图案的两个相邻晶体管共享相同 第二区域连接到地线并且连接到从字线到另一个的不同位线。

公开(公告)号：US07184299B2

公开(公告)日：2007-02-27

申请号：US10726263

申请日：2003-12-02

Applicant: Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C11/00

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18′).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

公开(公告)号：US20060256604A1

公开(公告)日：2006-11-16

申请号：US11433046

申请日：2006-05-12

Applicant: Francois Jacquet

Inventor： Francois Jacquet

IPC: G11C17/00

CPC classification number: G11C17/00 ,  G11C7/18

Abstract: Bit lines (BL0, BL0R, BL1, BL1R, . . . ) of a ROM memory array with differential detection reading are arranged within two overlaid metallization levels so as to increase the read reliability of binary values stored in the array. The ROM array is divided into matrix segments (100, 101, . . . ) aligned parallel to the bit lines. The bit lines are shifted horizontally and/or vertically within transition regions (T) located between the segments of matrix, by effecting circular permutations between the positions of the bit lines that are divided up into groups of four.

Abstract translation: 具有差分检测读取的ROM存储器阵列的位线（BL 0，BL 0 R，BL 1，BL 1 R，...）被布置在两个重叠的金属化电平内，以便增加存储在 数组。 ROM阵列被分成与位线平行排列的矩阵段（100,101 ......）。 位线在位于矩阵的段之间的过渡区域（T）内水平和/或垂直移位，通过在被划分成四组的位线之间进行圆形排列。

公开(公告)号：US20060187702A1

公开(公告)日：2006-08-24

申请号：US11343920

申请日：2006-01-30

Applicant: Francois Jacquet

Inventor： Francois Jacquet

IPC: G11C11/00

CPC classification number: G11C11/419 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/002

Abstract: A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

公开(公告)号：US08482964B2

公开(公告)日：2013-07-09

申请号：US12645039

申请日：2009-12-22

Applicant: Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。