公开(公告)号：US5003371A

公开(公告)日：1991-03-26

申请号：US264205

申请日：1988-10-28

Applicant: Francois Tailliet ,  Jacek Kowalski

Inventor： Francois Tailliet ,  Jacek Kowalski

IPC: H01L27/08 ,  G11C17/18 ,  H01H37/76 ,  H01H85/00 ,  H01H85/02 ,  H01H85/46 ,  H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L29/74

CPC classification number: G11C17/18 ,  H01L23/5256 ,  H01L2924/0002

Abstract: The melting of a fuse of a CMOS type integrated circuit is caused by using the existence of a stray thyristor created in the neighborhood of the boundaries of pads made in a substrate. This stray thyristor is triggered by artificially making the potential drop in an intermediate region of the pad. The thyristor always comes on suddenly, the current that flows through the thyristor is very high and the phenomenon stops spontaneously when the fuse is melted.

Abstract translation: CMOS型集成电路的熔丝的熔化是由于在衬底中形成的焊盘的边界附近产生的杂散晶闸管的存在引起的。 这种杂散晶闸管是通过人为地在焊盘的中间区域产生潜在的下降来触发的。 晶闸管总是突然出现，流过晶闸管的电流非常高，当保险丝熔化时，这种现象自发停止。

公开(公告)号：US08891310B2

公开(公告)日：2014-11-18

申请号：US13610425

申请日：2012-09-11

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0425 ,  G11C16/08

Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.

Abstract translation: 本公开涉及一种电可擦除和可编程存储器，其包括与第一和第二控制栅极晶体管并联的至少一个存储单元字，以将控制栅极电压施加到该单元的存储单元。 存储器还包括通过第一限流器向第一控制栅极晶体管的控制端提供第一控制电压的第一控制电路，以及向第二控制栅极的控制端提供第二控制电压的第二控制电路 晶体管通过第二限流器。

公开(公告)号：US08802455B2

公开(公告)日：2014-08-12

申请号：US13435201

申请日：2012-03-30

Applicant: Francois Tailliet ,  Marc Battista ,  Luc Wuidart

Inventor： Francois Tailliet ,  Marc Battista ,  Luc Wuidart

IPC: H01L21/66

CPC classification number: H04W12/04 ,  G01R31/31719 ,  G06F21/70 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H04W12/08 ,  H01L2924/00

Abstract: A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer.

Abstract translation: 提供了一种用于制造包括由划线分开的多个芯片的晶片的工艺。 该方法包括使用秘密密钥将晶片上的至少一个芯片锁定，并将秘密密钥写入存在于晶片上的至少一个存储器。

公开(公告)号：US08792262B2

公开(公告)日：2014-07-29

申请号：US13482727

申请日：2012-05-29

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C7/02

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A method of programming memory cells in a nonvolatile memory, includes applying a programming voltage to a first bitline and setting a second bitline in a floating state. The method further includes applying a compensation voltage to a shield conductive line coupled to the bitline set in the floating state, and setting in the floating state a shield conductive line coupled to the bitline receiving the programming voltage. The method is applicable to the reduction of the parasitic programming phenomena of memory cells by capacitive coupling between bitlines.

Abstract translation: 一种对非易失性存储器中的存储器单元进行编程的方法，包括将编程电压施加到第一位线，并将浮置状态下的第二位线设置。 该方法还包括将补偿电压施加到耦合到处于浮置状态的位线的屏蔽导线，并将浮动状态设置为耦合到接收编程电压的位线的屏蔽导线。 该方法适用于通过位线之间的电容耦合来减少存储器单元的寄生编程现象。

公开(公告)号：US08717820B2

公开(公告)日：2014-05-06

申请号：US13599222

申请日：2012-08-30

Applicant: Francois Tailliet ,  Yvon Bahout

Inventor： Francois Tailliet ,  Yvon Bahout

IPC: G11C16/04 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C8/12

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract translation: 一种用于电气编程非易失性存储器的方法，其中编程周期包括对应于存储器平面的第一行和列的初始地址的存储器单元的先前寻址。 该方法可以包括在达到第一行的末尾时寻址第二连续行中的存储器单元，以在两个连续行中具有连续和增加的地址的位上存储数据。

公开(公告)号：US08572351B2

公开(公告)日：2013-10-29

申请号：US12902707

申请日：2010-10-12

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G06F13/00

CPC classification number: G11C8/06 ,  G11C8/04 ,  G11C16/08

Abstract: The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical address received by m/2k.

Abstract translation: 存储器件包括物理存储器平面（PMP），包括沿着第一方向延伸的m个第一物理线（RGP1i）和沿着第二方向延伸的n个第二物理线（RGP2j）;接收装置，用于接收指定 第一逻辑线（RG1i）和矩阵逻辑存储器平面（PML）的第二逻辑线（RG2j），具有沿着第一方向延伸的2p个第一逻辑线和沿着第二方向延伸的2q个第二逻辑线，其中m和n 各自不同于2的幂，m是2k的倍数，k小于或等于p，并且m和n的乘积等于2p + q以上的最接近的整数，并且其包括用于 根据接收到的所述逻辑地址的内容和一部分的所述逻辑地址的剩余部分，寻址被配置为寻址第一物理线和第二物理线的一部分的物理存储器平面（PMP） 公司 这个逻辑地址由m / 2k接收。

公开(公告)号：US08351261B2

公开(公告)日：2013-01-08

申请号：US12907746

申请日：2010-10-19

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C11/34

CPC classification number: G11C5/145 ,  G11C7/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/14

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract translation: 本公开涉及一种用于向至少一个集成电路提供用于擦除和/或编程存储器的高电压的装置。 该装置包括与集成电路的至少一个接触端子相连的至少一个接触端子，用于监视由集成电路接收的数据信号并在数据信号中检测存储器的写入命令的监视器，以及用于 当监视器检测到存储器的写入命令时，将高电压施加到集成电路的端子。

公开(公告)号：US20120307563A1

公开(公告)日：2012-12-06

申请号：US13482727

申请日：2012-05-29

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C16/10

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A method of programming memory cells in a nonvolatile memory, includes applying a programming voltage to a first bitline and setting a second bitline in a floating state. The method further includes applying a compensation voltage to a shield conductive line coupled to the bitline set in the floating state, and setting in the floating state a shield conductive line coupled to the bitline receiving the programming voltage. The method is applicable to the reduction of the parasitic programming phenomena of memory cells by capacitive coupling between bitlines.

Abstract translation: 一种对非易失性存储器中的存储器单元进行编程的方法，包括将编程电压施加到第一位线，并将浮置状态下的第二位线设置。 该方法还包括将补偿电压施加到耦合到处于浮置状态的位线的屏蔽导线，并将浮动状态设置为耦合到接收编程电压的位线的屏蔽导线。 该方法适用于通过位线之间的电容耦合来减少存储器单元的寄生编程现象。

公开(公告)号：US08228732B2

公开(公告)日：2012-07-24

申请号：US12613341

申请日：2009-11-05

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C11/34

CPC classification number: G11C16/0425 ,  G11C16/08 ,  G11C16/26

Abstract: The disclosure relates to an electrically erasable and programmable memory, comprising memory cells arranged in bit lines and word lines transverse to bit lines, wherein each memory cell may be in a programmed or erased state, the memory comprising memory cell selection circuits configured to memorize and read data bits in two memory cells belonging to different bit lines and different word lines, and to avoid a memory cell from being written or read by mistake in another state than a default state after a gate oxide breakdown of a transistor of the memory, and a read circuit to determine a data bit to be read in the memory according to the states of the two memory cells memorizing the data bit.

Abstract translation: 本公开涉及一种电可擦除和可编程存储器，其包括以位线和横向于位线的字线布置的存储器单元，其中每个存储器单元可以处于编程或擦除状态，所述存储器包括存储器单元选择电路，其被配置为存储和 在属于不同位线和不同字线的两个存储单元中读取数据位，并且避免存储器单元在存储器的晶体管的栅极氧化物击穿之后的另一状态下被错误地写入或读取，而不是默认状态;以及 读取电路，用于根据存储数据位的两个存储单元的状态确定要在存储器中读取的数据位。

公开(公告)号：US20110255560A1

公开(公告)日：2011-10-20

申请号：US13140561

申请日：2009-12-10

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H04J3/06

CPC classification number: G06F13/4291

Abstract: A method and a system of multichannel transmission over a twin-wire bus including a data signal and a synchronization signal, data of a first channel being transmitted by a state coding of the data signal for a time period containing a first state of the synchronization signal, data of a second channel being transmitted by pulse coding outside of said period.

Abstract translation: 一种包括数据信号和同步信号的双线总线上的多信道传输的方法和系统，通过数据信号的状态编码在包含同步信号的第一状态的时段内发送第一信道的数据 ，在所述周期之外通过脉冲编码发送的第二信道的数据。