利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

96 条记录 (耗时 0.031 秒)

    Bidirectional port with clock channel used for synchronization
    21.
    发明授权
    Bidirectional port with clock channel used for synchronization 有权
    具有时钟通道的双向端口用于同步

    公开(公告)号：US06791356B2

    公开(公告)日：2004-09-14

    申请号：US09894865

    申请日：2001-06-28

    申请人： Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin

    发明人： Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin

    IPC分类号： H03K190175

    CPC分类号： G06F13/4077

    摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

    摘要翻译： 耦合到总线的同时双向端口组合同步电路和时钟电路。 同步和时钟电路将端口与耦合到同一总线的另一个同时的数据端口同步。 提供能够打开和关闭的时钟驱动器电路。 在同步之前，时钟驱动程序关闭，并且在同步之后，时钟驱动程序处于打开状态。 时钟接收器电路包括用于检测输入时钟信号的存在的时钟检测电路。 当集成电路准备好通信时，输出时钟驱动器导通，监视时钟检测电路，以确定何时接收输入时钟信号。 当输出时钟驱动器都打开并且正在接收输入时钟信号时，同时双向端口被同步，并且可以发生集成电路之间的通信。

    Integrated circuit stubs in a point-to-point system
    22.
    发明授权
    Integrated circuit stubs in a point-to-point system 有权
    集成电路存根在点对点系统中

    公开(公告)号：US06747474B2

    公开(公告)日：2004-06-08

    申请号：US09797480

    申请日：2001-02-28

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K1716

    CPC分类号： H04L5/14 ,  H03K19/01759 ,  H04L25/0278 ,  H04L25/24

    摘要： In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.

    摘要翻译： 在一些实施例中，本发明涉及串联耦合的多个集成电路短截线。 所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体，用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体 电路芯片。 集成电路短截线包括耦合到第一，第二和第三导体的第一驱动器和第二驱动器，其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上，并且第二驱动器从第一导体接收信号 并将它们驱动到第三导体上。

    Apparatus for testing simultaneous bi-directional I/O circuits
    25.
    发明授权
    Apparatus for testing simultaneous bi-directional I/O circuits 失效
    用于测试同时双向I / O电路的装置

    公开(公告)号：US06639426B2

    公开(公告)日：2003-10-28

    申请号：US10046448

    申请日：2001-10-29

    申请人： Matthew B. Haycock ,  Stephen R. Mooney

    发明人： Matthew B. Haycock ,  Stephen R. Mooney

    IPC分类号： H03K1900

    CPC分类号： H04L1/243

    摘要： A simultaneous bi-directional I/O circuit includes a first MUX in the reference select circuitry and a second, matching MUX in the pre-driver stage of the output buffer. In normal mode, the first MUX passes the driven data output signal, which controls the threshold of the differential receiver circuit between two different non-zero voltage levels, so that the receiver circuit can properly decode an incoming signal at the I/O node or pin. In an AC switching state or loopback test mode, the first MUX de-selects the driven data output signal from controlling the receiver circuit. This allows the receiver circuit to decode outgoing data that is being looped back as incoming data. The second MUX enables the reference select circuitry to switch at a rate that matches the output slew rate in order to provide high-speed operation. Also described are an electronic system, a data processing system, and various methods of testing simultaneous bi-directional I/O circuits.

    摘要翻译： 同时双向I / O电路包括参考选择电路中的第一MUX和输出缓冲器的前驱动器级中的第二匹配MUX。 在正常模式下，第一MUX通过驱动数据输出信号，该信号控制差分接收器电路的阈值在两个不同的非零电压电平之间，使得接收机电路可以正确地解码I / O节点处的输入信号， 销。 在交流切换状态或环回测试模式中，第一MUX从控制接收机电路中取消驱动数据输出信号的选择。 这允许接收器电路将作为输入数据循环的输出数据进行解码。 第二MUX使参考选择电路以与输出转换速率匹配的速率切换，以便提供高速操作。 还描述了电子系统，数据处理系统和测试同时双向I / O电路的各种方法。

    Current mode bidirectional port with data channel used for synchronization
    26.
    发明授权
    Current mode bidirectional port with data channel used for synchronization 有权
    电流模式双向端口，数据通道用于同步

    公开(公告)号：US06597198B2

    公开(公告)日：2003-07-22

    申请号：US09972327

    申请日：2001-10-05

    申请人： Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin

    发明人： Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin

    IPC分类号： H03K190175

    CPC分类号： H04L25/45 ,  H03K19/018592 ,  H04L7/0004

    摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a data transceiver circuit. The combination data and synchronization transceiver circuit synchronizes the port with another simultaneous bidirectional port coupled to the same bus. The combination data and synchronization transceiver circuit includes a driver with a variable output current and a variable output resistance. Prior to synchronization, the driver has a low output current and low output resistance. When the simultaneous bidirectional port is ready to communicate, the variable output resistance is increased. When both simultaneous bidirectional ports are ready, the variable output resistance is set to properly terminate the line, and the variable output current is set to provide a desired voltage swing.

    摘要翻译： 耦合到总线的同时双向端口组合同步电路和数据收发器电路。 组合数据和同步收发器电路将端口与耦合到同一总线的另一个同时双向端口同步。 组合数据和同步收发器电路包括具有可变输出电流和可变输出电阻的驱动器。 在同步之前，驱动器具有低输出电流和低输出电阻。 当同时双向端口准备通信时，可变输出电阻增加。 当两个同时双向端口准备就绪时，可变输出电阻被设置为适当地终止线路，并且可变输出电流被设置为提供期望的电压摆幅。