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    Simultaneous transmission and reception of signals in different frequency bands over a bus line
    1.
    发明授权
    Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
    在总线上同时发送和接收不同频段的信号

    公开(公告)号：US07177288B2

    公开(公告)日：2007-02-13

    申请号：US09998008

    申请日：2001-11-28

    申请人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    发明人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    IPC分类号： H04L5/14

    CPC分类号： H04L5/1423

    摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

    摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。

    Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit
    2.
    发明授权
    Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit 失效
    在数据接收器电路中使用可变偏移比较器的传输线模拟信号的电压裕度测试

    公开(公告)号：US06653893B2

    公开(公告)日：2003-11-25

    申请号：US09967666

    申请日：2001-09-28

    申请人： Bryan K. Casper ,  Stephen R. Mooney ,  Matthew B. Haycock

    发明人： Bryan K. Casper ,  Stephen R. Mooney ,  Matthew B. Haycock

    IPC分类号： H03F345

    CPC分类号： H03F3/45183 ,  H03F3/45672 ,  H03F2203/45371

    摘要： A data receiver circuit having a comparator that exhibits substantially variable offset that is controllable to represent a variable reference level, without a separate input to receive a reference voltage level. The comparator output provides an indication of the comparison between a fixed voltage level applied to its differential signal input and the variable reference level. While changing an offset code that is fed to an offset control input of the comparator, and while applying a fixed voltage level that represents a symbol in the transmission line analog signal, a value of the offset code which causes the output of the comparator to change states is captured. A similar process may be repeated for different symbol values that can be transmitted, such that an indication of the voltage margin may be obtained as a difference between two captured offset codes. Circuitry to perform the process may be provided on-chip to the receiver circuit.

    摘要翻译： 一种具有比较器的数据接收器电路，其具有可变的偏移，其可控制以表示可变参考电平，而没有单独的输入以接收参考电压电平。 比较器输出提供了施加到其差分信号输入的固定电压电平与可变参考电平之间的比较的指示。 在改变馈送到比较器的偏移控制输入的偏移代码的同时，在施加表示传输线模拟信号中的符号的固定电压电平的同时，使比较器的输出变化的偏移代码的值 状态被捕获。 可以对可以发送的不同符号值重复类似的过程，使得可以获得电压余量的指示作为两个所捕获的偏移码之间的差。 执行该处理的电路可以片上提供给接收器电路。

    Using a timing strobe for synchronization and validation in a digital logic device
    3.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

    Biased control loop circuit for setting impedance of output driver
    4.
    发明授权
    Biased control loop circuit for setting impedance of output driver 有权
    用于设置输出驱动器阻抗的偏置控制回路电路

    公开(公告)号：US06424175B1

    公开(公告)日：2002-07-23

    申请号：US09659499

    申请日：2000-09-11

    申请人： Sriram R. Vangal ,  Matthew B. Haycock ,  Stephen R. Mooney

    发明人： Sriram R. Vangal ,  Matthew B. Haycock ,  Stephen R. Mooney

    IPC分类号： H03K1716

    CPC分类号： H03K19/00384

    摘要： A biased control loop for setting the impedance of an output driver includes a dummy driver having a variable output impedance, a sample and compare circuit to compare the output impedance of dummy output driver to a reference, and an up/down counter to modify the impedance. When the loop is locked, an error signal alternates positive and negative about a reference value. A digital filter produces a filtered version of the error signal with an apparent error value that does not alternate. The digital filter has a biased lock circuit that guarantees that the apparent error does not alternate. A simultaneous bidirectional port includes an output driver and the biased control loop to set the output driver impedance. When the output driver drives a bidirectional line and serves as a termination impedance for another driver, the reduced apparent error variation provides improved impedance matching.

    摘要翻译： 用于设置输出驱动器的阻抗的偏置控制环路包括具有可变输出阻抗的虚拟驱动器，用于将虚拟输出驱动器的输出阻抗与参考值进行比较的采样和比较电路以及用于修改阻抗的上/下计数器 。 当环路被锁定时，错误信号会围绕参考值交替正负。 数字滤波器产生误差信号的滤波版本，具有不交替的明显误差值。 数字滤波器具有偏置的锁定电路，保证视在误差不会交替。 同时双向端口包括输出驱动器和偏置控制环路以设置输出驱动器阻抗。 当输出驱动器驱动双向线并用作另一个驱动器的终端阻抗时，减小的视差误差提供改进的阻抗匹配。

    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe
    5.
    发明授权
    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权
    具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化

    公开(公告)号：US06373289B1

    公开(公告)日：2002-04-16

    申请号：US09752895

    申请日：2000-12-26

    申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    IPC分类号： H03K1900

    CPC分类号： H03L7/0812 ,  H03K5/135 ,  H04L25/242

    摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

    摘要翻译： 频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。 下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。 受控延迟基本上等于锁存器的设定时间。 耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。 输出驱动器耦合到锁存器和延迟元件的输出。

    Impedance control circuit
    7.
    发明授权
    Impedance control circuit 失效
    阻抗控制电路

    公开(公告)号：US6087847A

    公开(公告)日：2000-07-11

    申请号：US902345

    申请日：1997-07-29

    申请人： Stephen R. Mooney ,  Matthew B. Haycock ,  Joseph T. Kennedy

    发明人： Stephen R. Mooney ,  Matthew B. Haycock ,  Joseph T. Kennedy

    IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/003

    CPC分类号： H03K19/017545 ,  H03K19/0005

    摘要： Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

    摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括：数字反馈控制电路，用于至少部分地基于调整了非数据信号输出缓冲器的阻抗来调整接口电路输出缓冲器的阻抗 耦合到外部阻抗。 简而言之，根据本发明的另一个实施例，一种数字调节接口电路输出缓冲器的阻抗的方法包括：数字调节耦合到外部阻抗的非数据信号输出缓冲器的阻抗，并数字调节阻抗 所述接口电路输出缓冲器至少部分地基于非数据信号输出缓冲器的数字调节阻抗。

    On-chip observability buffer to observer bus traffic
    9.
    发明授权
    On-chip observability buffer to observer bus traffic 失效
    观察员总线流量的片上可观察性缓冲区

    公开(公告)号：US07171510B2

    公开(公告)日：2007-01-30

    申请号：US09752880

    申请日：2000-12-28

    申请人： Matthew B. Haycock ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Matthew B. Haycock ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： G06F13/36 ,  G06F13/14 ,  G06F11/00 ,  G01R31/00 ,  G01R31/14

    CPC分类号： G06F11/221

    摘要： The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.

    摘要翻译： 本发明在一个实施例中提供了一种用于非干涉地观察，回送和读取由总线和无线通信之一发送的信号而不干扰总线的电气特性而不增加总线等待时间并且不增加信号不连续性的装置，方法和装置 。 在一方面，具有触发器的缓冲器与连接到存储器总线的部件耦合，缓冲器将信号回送到可观测端口，并且诊断装置读取回送信号。 一方面，总线是具有三元逻辑电平的同时双向（SBD）总线之一，单端总线，差分总线，光耦合总线，芯片组总线，前端总线，输入/输出（ I / O）总线，外设组件接口（PCI）总线和工业标准架构（ISA）总线。 在一个方面，缓冲器回波频率在500MHz之间的总线信号。 和5 GHz。 在一方面，缓冲器响应具有至少5GHz频率的总线信号。

    Transition reduction encoder using current and last bit sets
    10.
    发明授权
    Transition reduction encoder using current and last bit sets 失效
    使用当前位和最后位的转换减速编码器

    公开(公告)号：US06538584B2

    公开(公告)日：2003-03-25

    申请号：US09752883

    申请日：2000-12-28

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03M700

    CPC分类号： G11C7/10

    摘要： In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

    摘要翻译： 在一些实施例中，本发明涉及包括第一组导体的电路，以承载当前位组和最后位组电路以保持并提供最后位组。 电路还包括耦合到互连导体的驱动器以提供从驱动器到互连导体的信号，以及用于接收最后位组和当前位组的编码器，并确定是提供当前位组还是当前位的编码版本 设置为司机。