公开(公告)号：US20190265779A1

公开(公告)日：2019-08-29

申请号：US16286138

申请日：2019-02-26

申请人： Anatoly Gelman ,  Taner Dosluoglu

发明人： Anatoly Gelman ,  Taner Dosluoglu

IPC分类号： G06F1/3296 ,  G06F1/12 ,  G06F1/324 ,  G06F1/28 ,  G06F1/08

摘要： Circuitry may monitor a processor supply voltage and pull power from the processor supply on a temporary basis when the supply voltage rises above predetermined levels. In some embodiments this may be done without explicit knowledge of a commanded supply voltage level for the processor.

公开(公告)号：US20130082738A1

公开(公告)日：2013-04-04

申请号：US13250042

申请日：2011-09-30

申请人： Anatoly Gelman

发明人： Anatoly Gelman

IPC分类号： H03K19/096

CPC分类号： G06F1/3237 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G11C7/222 ,  Y02D10/126 ,  Y02D10/128

摘要： Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking.

摘要翻译： 提供了方法，系统和计算机程序产品来实现双数据速率（DDR）逻辑的时钟门控。 在传统的单数据速率（SDR）时钟门控中，禁止时钟将时钟逻辑电平保持为预定义值，可能导致逻辑转换，这将被错误地解释为DDR逻辑的正常时钟转换。 也可以使用类似的技术将SDR时钟转换为用于DDR逻辑的半频DDR时钟，实现DDR时钟的能量效率。

公开(公告)号：US08171260B2

公开(公告)日：2012-05-01

申请号：US12489889

申请日：2009-06-23

申请人： Anatoly Gelman ,  Russell Lawrence Schnapp

发明人： Anatoly Gelman ,  Russell Lawrence Schnapp

IPC分类号： G06F9/38

CPC分类号： G06F9/3844

摘要： The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome. Both the decode and execution pipelines include correction capabilities for modifying the block branch target buffer dependent on the results of the instruction decode and execution and can include a mechanism to correct malformed instructions.

摘要翻译： 本发明提供了一种用于在处理器中进行分支预测的方法和装置。 在解码指令之前，在流水线处理的早期阶段使用取出块分支目标缓冲器，其存储关于指令存储器的“块”的控制传送指令的信息。 指令存储器块由提取块分支目标缓冲器中的块条目表示。 块条目表示一个记录的控制传送指令（例如分支指令）和一组先前的指令，直到固定的最大长度N.索引到提取块分支目标缓冲器中产生一个答案，无论块条目是否表示 存储器，其包含先前执行的控制传递指令，表示包含由该块表示的指令的存储器的量的长度值以及终止块，其目标和结果的控制传送指令的类型的指示符。 解码和执行流水线都包括用于根据指令解码和执行的结果修改块分支目标缓冲器的校正能力，并且可以包括校正畸形指令的机制。

公开(公告)号：US20060036836A1

公开(公告)日：2006-02-16

申请号：US11252029

申请日：2005-10-17

申请人： Anatoly Gelman ,  Russell Schnapp

发明人： Anatoly Gelman ,  Russell Schnapp

IPC分类号： G06F15/00

CPC分类号： G06F9/3844

摘要： The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome. Both the decode and execution pipelines include correction capabilities for modifying the block branch target buffer dependent on the results of the instruction decode and execution and can include a mechanism to correct malformed instructions.

摘要翻译： 本发明提供了一种用于在处理器中进行分支预测的方法和装置。 在解码指令之前，在流水线处理的早期阶段使用取出块分支目标缓冲器，其存储关于指令存储器的“块”的控制传送指令的信息。 指令存储器块由提取块分支目标缓冲器中的块条目表示。 块条目表示一个记录的控制传送指令（例如分支指令）和一组先前的指令，直到固定的最大长度N.索引到提取块分支目标缓冲器中产生一个答案，无论块条目是否表示 存储器，其包含先前执行的控制传递指令，表示包含由该块表示的指令的存储器的量的长度值以及终止块，其目标和结果的控制传送指令的类型的指示符。 解码和执行流水线都包括用于根据指令解码和执行的结果修改块分支目标缓冲器的校正能力，并且可以包括校正畸形指令的机制。

公开(公告)号：US06581138B2

公开(公告)日：2003-06-17

申请号：US09514973

申请日：2000-02-29

申请人： Anatoly Gelman

发明人： Anatoly Gelman

IPC分类号： G06F928

CPC分类号： G06F9/3806 ,  G06F12/0862 ,  G06F12/0875

摘要： The invention provides a method and apparatus for optimizing instruction prefetch and caching in a processor. In the preferred embodiment, a path prediction circuit maintains information about which cache lines are likely to be executed in the future. This information is used to independently fetch the predicted cache lines, store them in a prefetch queue, and load them in to the instruction cache as instructions contained in these lines are about to be decoded by the processor. A plurality of cache lines can be in the process of being simultaneously fetched from main memory to load the prefetch queue.

摘要翻译： 本发明提供一种用于在处理器中优化指令预取和高速缓存的方法和装置。 在优选实施例中，路径预测电路维护关于将来可能执行哪些高速缓存行的信息。 该信息用于独立地获取预测的高速缓存行，将它们存储在预取队列中，并将它们加载到指令高速缓存中，因为这些行中包含的指令即将被处理器解码。 多个高速缓存线可以处于从主存储器同时提取以加载预取队列的过程中。