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27 条记录 (耗时 0.012 秒)

    Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address
    3.
    发明授权
    Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address 有权
    根据存储在由抓取地址索引的分支目标缓冲区中的分支预测和大小指示符，将内存行中的所有或部分指令取出到分支指令

    公开(公告)号：US07552314B2

    公开(公告)日：2009-06-23

    申请号：US11252029

    申请日：2005-10-17

    申请人： Anatoly Gelman ,  Russell Schnapp

    发明人： Anatoly Gelman ,  Russell Schnapp

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844

    摘要： The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome. Both the decode and execution pipelines include correction capabilities for modifying the block branch target buffer dependent on the results of the instruction decode and execution and can include a mechanism to correct malformed instructions.

    摘要翻译： 本发明提供了一种用于在处理器中进行分支预测的方法和装置。 在解码指令之前，在流水线处理的早期阶段使用取出块分支目标缓冲器，其存储关于指令存储器的“块”的控制传送指令的信息。 指令存储器块由提取块分支目标缓冲器中的块条目表示。 块条目表示一个记录的控制传输指令（例如分支指令）和一组先前的指令，直到固定的最大长度N.索引到提取块分支目标缓冲器中产生一个答案，无论块条目是否表示 存储器，其包含先前执行的控制传递指令，表示包含由该块表示的指令的存储器的量的长度值以及终止块，其目标和结果的控制传送指令的类型的指示符。 解码和执行流水线都包括用于根据指令解码和执行的结果修改块分支目标缓冲器的校正能力，并且可以包括校正畸形指令的机制。

    Radio frequency integrated circuit having frequency dependent noise mitigation with spectrum spreading
    4.
    发明申请
    Radio frequency integrated circuit having frequency dependent noise mitigation with spectrum spreading 有权
    射频集成电路具有频谱扩展的频率相关噪声抑制

    公开(公告)号：US20080024339A1

    公开(公告)日：2008-01-31

    申请号：US11641562

    申请日：2006-12-18

    申请人： Frederic Christian Marc Hayem ,  Hooman Darabi ,  Mike (Hon Fai) Chu ,  Anatoly Gelman ,  Kiran Puttegowda ,  Ahmadreza (Reza) Rofougaran ,  Maryam Rofougaran ,  Claude G. Hayek ,  Nelson R. Sollenberger ,  Ronish Patel

    发明人： Frederic Christian Marc Hayem ,  Hooman Darabi ,  Mike (Hon Fai) Chu ,  Anatoly Gelman ,  Kiran Puttegowda ,  Ahmadreza (Reza) Rofougaran ,  Maryam Rofougaran ,  Claude G. Hayek ,  Nelson R. Sollenberger ,  Ronish Patel

    IPC分类号： H03M1/00

    CPC分类号： H04B15/06

    摘要： A radio frequency integrated circuit (RFIC) includes a low noise amplifier that amplifies an inbound radio frequency (RF) signal to produce an amplified RF signal. A down conversion module converts the amplified RF signal to a down converted signal based on a local oscillation. An analog to digital conversion (ADC) module coupled to convert the down converted signal into a digital signal. A baseband processing module converts the digital signal into inbound data, wherein at least one function of the baseband processing module is clocked by a plurality of baseband clock signals A clock module produces the plurality of baseband clock signals, wherein the clock module detects an interference condition when frequency dependent noise components associated with at least one of the plurality of baseband clock signals are inside a frequency band associated with the inbound RF signal, and spreads the spectrum of the at least one of the plurality of baseband clock signals when the interference condition is detected.

    摘要翻译： 射频集成电路（RFIC）包括放大入射射频（RF）信号以产生放大的RF信号的低噪声放大器。 降频转换模块基于本地振荡将放大的RF信号转换为下变频信号。 模数转换（ADC）模块耦合以将下变频信号转换为数字信号。 基带处理模块将数字信号转换为入站数据，其中基带处理模块的至少一个功能由多个基带时钟信号A计时。时钟模块产生多个基带时钟信号，其中时钟模块检测干扰条件 当与所述多个基带时钟信号中的至少一个相关联的频率相关噪声分量在与所述入站RF信号相关联的频带内时，并且当所述干扰条件是所述干扰条件是时，扩展所述多个基带时钟信号中的至少一个的频谱 检测到。

    Head up display mechanism
    6.
    发明授权
    Head up display mechanism 失效
    抬头显示机制

    公开(公告)号：US07570429B2

    公开(公告)日：2009-08-04

    申请号：US11595501

    申请日：2006-11-09

    申请人： Eyal Maliah ,  Shahar Hertz ,  Anatoly Gelman

    发明人： Eyal Maliah ,  Shahar Hertz ,  Anatoly Gelman

    IPC分类号： G02B27/14

    CPC分类号： G02B27/0149 ,  G02B2027/0156

    摘要： A Head up display (HUD) calibration assembly is designed for coupling a HUD system with the inner walls of a vehicle, and adjusting the orientation of the HUD system. The HUD calibration assembly includes a mounting tray for coupling with a HUD projector and with a HUD combiner deployment mechanism. The mounting tray includes a plurality of adjustment interface planes, each of which includes a locking screw opening, and a plurality of adjustment assemblies, each coupled with the vehicle in a respective separate anchoring location, locking the mounting tray at the desired position and orientation.

    摘要翻译： 抬头显示（HUD）校准组件设计用于将HUD系统与车辆内壁相连，并调整HUD系统的方向。 HUD校准组件包括用于与HUD投影仪和HUD组合器部署机构耦合的安装托盘。 安装托盘包括多个调节接口平面，每个调整接口平面包括锁定螺钉开口和多个调节组件，每个调节组件在相应的单独的锚固位置中与车辆联接，将安装托盘锁定在期望的位置和方向。

    DOUBLE DATA RATE CLOCK GATING
    9.
    发明申请
    DOUBLE DATA RATE CLOCK GATING 有权
    双数据速率时钟增益

    公开(公告)号：US20130082738A1

    公开(公告)日：2013-04-04

    申请号：US13250042

    申请日：2011-09-30

    申请人： Anatoly Gelman

    发明人： Anatoly Gelman

    IPC分类号： H03K19/096

    CPC分类号： G06F1/3237 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G11C7/222 ,  Y02D10/126 ,  Y02D10/128

    摘要： Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking.

    摘要翻译： 提供了方法，系统和计算机程序产品来实现双数据速率（DDR）逻辑的时钟门控。 在传统的单数据速率（SDR）时钟门控中，禁止时钟将时钟逻辑电平保持为预定义值，可能导致逻辑转换，这将被错误地解释为DDR逻辑的正常时钟转换。 也可以使用类似的技术将SDR时钟转换为用于DDR逻辑的半频DDR时钟，实现DDR时钟的能量效率。

    Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address
    10.
    发明授权
    Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address 有权
    根据存储在由抓取地址索引的分支目标缓冲区中的分支预测和大小指示符，将内存行中的所有或部分指令取出到分支指令

    公开(公告)号：US08171260B2

    公开(公告)日：2012-05-01

    申请号：US12489889

    申请日：2009-06-23

    申请人： Anatoly Gelman ,  Russell Lawrence Schnapp

    发明人： Anatoly Gelman ,  Russell Lawrence Schnapp

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844

    摘要： The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome. Both the decode and execution pipelines include correction capabilities for modifying the block branch target buffer dependent on the results of the instruction decode and execution and can include a mechanism to correct malformed instructions.

    摘要翻译： 本发明提供了一种用于在处理器中进行分支预测的方法和装置。 在解码指令之前，在流水线处理的早期阶段使用取出块分支目标缓冲器，其存储关于指令存储器的“块”的控制传送指令的信息。 指令存储器块由提取块分支目标缓冲器中的块条目表示。 块条目表示一个记录的控制传送指令（例如分支指令）和一组先前的指令，直到固定的最大长度N.索引到提取块分支目标缓冲器中产生一个答案，无论块条目是否表示 存储器，其包含先前执行的控制传递指令，表示包含由该块表示的指令的存储器的量的长度值以及终止块，其目标和结果的控制传送指令的类型的指示符。 解码和执行流水线都包括用于根据指令解码和执行的结果修改块分支目标缓冲器的校正能力，并且可以包括校正畸形指令的机制。