公开(公告)号：US09081708B2

公开(公告)日：2015-07-14

申请号：US13679481

申请日：2012-11-16

申请人： Fuchen Mu ,  Yanzhou Wang

发明人： Fuchen Mu ,  Yanzhou Wang

IPC分类号： G11C29/50 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G11C29/50004 ,  G11C2029/0411

摘要： In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.

摘要翻译： 根据至少一个实施例，描述了一种用于提高校正存储器件中的错误的能力的方法和装置。 至少一个实施例提供了一种挽救部件的方法，即使它具有来自相同ECC部分的双位或多位错误，从而提高产品可靠性并延长产品寿命。 在正常读取期间，如果发生双位或多位错误，哪个ECC可以检测到但无法修复，则通过调整读取电压电平并再次读取来确定正确的读取电平（因此， 读正确值）。 该动态读取方案可以应用于擦除状态或程序状态的外部位。 它也可以用于单个位方案以最小化ECC发生并节省ECC容量。

公开(公告)号：US08995202B2

公开(公告)日：2015-03-31

申请号：US13476711

申请日：2012-05-21

申请人： Fuchen Mu ,  Paul A Bogucki ,  Chen He

发明人： Fuchen Mu ,  Paul A Bogucki ,  Chen He

IPC分类号： G11C11/34 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

摘要翻译： 用于检测非易失性存储器的泄漏位的技术包括擦除非易失性存储器的单元。 在擦除之后，对单元施加偏压应力。 在向单元施加偏置应力之后对单元执行擦除验证操作。 最后，基于各个单元的阈值电压是否低于擦除验证电平，确定单元是否通过或者失败擦除验证操作。

公开(公告)号：US20090231925A1

公开(公告)日：2009-09-17

申请号：US12048683

申请日：2008-03-14

申请人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

发明人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

IPC分类号： G11C16/06 ,  G11C16/26

CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C11/5642

摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.

摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。

公开(公告)号：US20140204678A1

公开(公告)日：2014-07-24

申请号：US13747504

申请日：2013-01-23

申请人： Fuchen Mu ,  Chen He

发明人： Fuchen Mu ,  Chen He

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3409 ,  G11C16/349

摘要： A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM.

摘要翻译： 公开了一种用于检测非易失性存储器（NVM）中的潜在慢位（例如，潜在慢擦除位）的方法和装置。 对擦除周期内的地址间的软编程脉冲的最大数进行计数。 根据至少一个实施例，对擦除周期期间的擦除脉冲进行计数。 根据各种实施例，确定最大数量的软编程脉冲是否以与先前擦除周期相比至少预定最小速率的速率增加，无论最大数量的软编程脉冲是否已经超过 预定阈值，擦除脉冲的数目是否与先前的擦除周期相比增加，或其组合。 响应于这样的确定，NVM将根据NVM中不存在或存在慢速位而通过或失败。

公开(公告)号：US08713406B2

公开(公告)日：2014-04-29

申请号：US13459344

申请日：2012-04-30

申请人： Fuchen Mu ,  Frank K. Baker, Jr. ,  Chen He

发明人： Fuchen Mu ,  Frank K. Baker, Jr. ,  Chen He

IPC分类号： G11C29/00

CPC分类号： G11C16/16 ,  G11C16/3481

摘要： A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

摘要翻译： 一种擦除非易失性半导体存储器件的方法，包括在擦除操作期间确定不能擦除验证的位单元数目。 位单元包括在位单元阵列中的位单元的子集中。 该方法还包括确定是否先前对位单元的子集执行纠错码（ECC）校正。 如果在预定数量的擦除脉冲之后无法擦除验证的比特单元的数量低于阈值并且还没有对比特单元的子集执行ECC校正，则擦除操作被认为是成功的。

公开(公告)号：US08830756B2

公开(公告)日：2014-09-09

申请号：US13747504

申请日：2013-01-23

申请人： Fuchen Mu ,  Chen He

发明人： Fuchen Mu ,  Chen He

IPC分类号： G11C16/04 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/3409 ,  G11C16/349

摘要： A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM.

摘要翻译： 公开了一种用于检测非易失性存储器（NVM）中的潜在慢位（例如，潜在慢擦除位）的方法和装置。 对擦除周期内的地址间的软编程脉冲的最大数进行计数。 根据至少一个实施例，对擦除周期期间的擦除脉冲进行计数。 根据各种实施例，确定最大数量的软编程脉冲是否以与先前擦除周期相比至少预定最小速率的速率增加，无论最大数量的软编程脉冲是否已经超过 预定阈值，擦除脉冲的数目是否与先前的擦除周期相比增加，或其组合。 响应于这样的确定，NVM将根据NVM中不存在或存在慢速位而通过或失败。

公开(公告)号：US07742340B2

公开(公告)日：2010-06-22

申请号：US12048683

申请日：2008-03-14

申请人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

发明人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C11/5642

摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.

摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。

公开(公告)号：US20140143630A1

公开(公告)日：2014-05-22

申请号：US13679481

申请日：2012-11-16

申请人： Fuchen Mu ,  Yanzhou Wang

发明人： Fuchen Mu ,  Yanzhou Wang

IPC分类号： G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G11C29/50004 ,  G11C2029/0411

摘要： In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.

摘要翻译： 根据至少一个实施例，描述了一种用于提高校正存储器件中的错误的能力的方法和装置。 至少一个实施例提供了一种挽救部件的方法，即使它具有来自相同ECC部分的双位或多位错误，从而提高产品可靠性并延长产品寿命。 在正常读取期间，如果发生双位或多位错误，哪个ECC可以检测到但无法修复，则通过调整读取电压电平并再次读取来确定正确的读取电平（因此， 读正确值）。 该动态读取方案可以应用于擦除状态或程序状态的外部位。 它也可以用于单个位方案以最小化ECC发生并节省ECC容量。

公开(公告)号：US20130290808A1

公开(公告)日：2013-10-31

申请号：US13459344

申请日：2012-04-30

申请人： Fuchen Mu ,  Frank K. Baker, JR. ,  Chen He

发明人： Fuchen Mu ,  Frank K. Baker, JR. ,  Chen He

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C16/16 ,  G11C16/3481

摘要： A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

摘要翻译： 一种擦除非易失性半导体存储器件的方法，包括在擦除操作期间确定不能擦除验证的位单元数目。 位单元包括在位单元阵列中的位单元的子集中。 该方法还包括确定是否先前对位单元的子集执行纠错码（ECC）校正。 如果在预定数量的擦除脉冲之后无法擦除验证的比特单元的数量低于阈值并且还没有对比特单元的子集执行ECC校正，则擦除操作被认为是成功的。

公开(公告)号：US08290759B1

公开(公告)日：2012-10-16

申请号：US12061531

申请日：2008-04-02

申请人： Fuchen Mu ,  Lifeng Wu

发明人： Fuchen Mu ,  Lifeng Wu

IPC分类号： G06F7/60 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A method of determining a Negative Bias Temperature Instability (NBTI) effect that combines degradation and recovery for dynamic operation of an integrated circuit (IC) includes: specifying one or more parameters for a degradation model for the IC during a stressed portion of a voltage cycle; specifying one or more parameters for a recovery model for the IC during an unstressed portion of the voltage cycle; determining a degradation value for the voltage cycle from the degradation model; determining a recovery value for the voltage cycle from the recovery model; determining an NBTI value that combines the degradation value and the recovery value for the voltage cycle; and saving at least one value for the NBTI value.

摘要翻译： 一种确定负偏压温度不稳定性（NBTI）效应的方法，其结合用于集成电路（IC）的动态操作的退化和恢复，包括：在电压周期的应力部分期间指定用于IC的劣化模型的一个或多个参数 ; 在电压循环的无应力部分期间指定用于IC的恢复模型的一个或多个参数; 确定来自劣化模型的电压循环的劣化值; 从恢复模型确定电压循环的恢复值; 确定组合所述劣化值和所述电压循环的恢复值的NBTI值; 并为NBTI值保存至少一个值。