公开(公告)号：US09666276B2

公开(公告)日：2017-05-30

申请号：US14266168

申请日：2014-04-30

申请人： Frank K. Baker, Jr.

发明人： Frank K. Baker, Jr.

IPC分类号： G11C5/06 ,  G11C14/00 ,  G11C13/00

CPC分类号： G11C14/009 ,  G11C5/06 ,  G11C13/0069 ,  G11C14/0081

摘要： A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.

公开(公告)号：US20150348595A1

公开(公告)日：2015-12-03

申请号：US14287463

申请日：2014-05-27

申请人： Frank K. Baker, JR. ,  Perry H. Pelley ,  Ravindraraj Ramaraju

发明人： Frank K. Baker, JR. ,  Perry H. Pelley ,  Ravindraraj Ramaraju

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C5/06 ,  G11C5/025 ,  G11C5/063 ,  G11C5/14 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.

摘要翻译： 存储单元包括具有耦合到第一电源轨的阴极和耦合到内部节点的阳极的第一双向电阻元件，具有耦合到内部节点的阴极的第二双向电阻元件和耦合到内部节点的阳极 第二电源轨，以及具有耦合到所述内部节点的控制电极的第一晶体管，耦合到第一位线的第一电流电极和耦合到第三电力轨的第二电流电极。

公开(公告)号：US08713406B2

公开(公告)日：2014-04-29

申请号：US13459344

申请日：2012-04-30

申请人： Fuchen Mu ,  Frank K. Baker, Jr. ,  Chen He

发明人： Fuchen Mu ,  Frank K. Baker, Jr. ,  Chen He

IPC分类号： G11C29/00

CPC分类号： G11C16/16 ,  G11C16/3481

摘要： A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

摘要翻译： 一种擦除非易失性半导体存储器件的方法，包括在擦除操作期间确定不能擦除验证的位单元数目。 位单元包括在位单元阵列中的位单元的子集中。 该方法还包括确定是否先前对位单元的子集执行纠错码（ECC）校正。 如果在预定数量的擦除脉冲之后无法擦除验证的比特单元的数量低于阈值并且还没有对比特单元的子集执行ECC校正，则擦除操作被认为是成功的。

公开(公告)号：US08669158B2

公开(公告)日：2014-03-11

申请号：US13780574

申请日：2013-02-28

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。 在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。 保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。

公开(公告)号：US08341372B2

公开(公告)日：2012-12-25

申请号：US12769795

申请日：2010-04-29

申请人： Ross S. Scouller ,  Frank K. Baker, Jr. ,  Venkatagiri Chandrasekaran

发明人： Ross S. Scouller ,  Frank K. Baker, Jr. ,  Venkatagiri Chandrasekaran

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/401 ,  G06F2212/7203

摘要： A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector.

摘要翻译： 系统具有具有用于存储信息的多个扇区的仿真存储器。 控制器计算所使用的地址数量除以仿真存储器的预定地址范围中的有效记录数。 计算未被用于存储信息的仿真存储器的当前使用空间中的剩余地址的量。 确定计算是否大于第一预定数量，以及剩余地址的数量是否大于第二预定数量。 如果分数都大于第一预定数量，并且剩余地址的量大于第二预定数量，则使用当前使用的仿真存储器的空间来响应任何后续的更新请求。 否则，通过将有效数据复制到可用扇区，需要对仿真存储器进行压缩。

公开(公告)号：US07764550B2

公开(公告)日：2010-07-27

申请号：US12277404

申请日：2008-11-25

申请人： Mohammed Suhail ,  Frank K. Baker, Jr. ,  Gowrishankar L. Chindalore

发明人： Mohammed Suhail ,  Frank K. Baker, Jr. ,  Gowrishankar L. Chindalore

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/10 ,  G11C16/349

摘要： A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.

摘要翻译： 包括非易失性存储单元的存储器系统。 存储器系统包括基于存储器系统的单元已经被擦除的次数将单元编程为第一阈值电压或第二阈值电压的程序电路。 在一个实施例中，当存储器系统的任何一组单元已被擦除特定次数时，阈值电压被降低。

公开(公告)号：US09318158B2

公开(公告)日：2016-04-19

申请号：US14287463

申请日：2014-05-27

申请人： Frank K. Baker, Jr. ,  Perry H. Pelley ,  Ravindraraj Ramaraju

发明人： Frank K. Baker, Jr. ,  Perry H. Pelley ,  Ravindraraj Ramaraju

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C13/00

CPC分类号： G11C5/06 ,  G11C5/025 ,  G11C5/063 ,  G11C5/14 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.

摘要翻译： 存储单元包括具有耦合到第一电源轨的阴极和耦合到内部节点的阳极的第一双向电阻元件，具有耦合到内部节点的阴极和耦合到内部节点的阳极的第二双向电阻元件 第二电源轨，以及具有耦合到所述内部节点的控制电极的第一晶体管，耦合到第一位线的第一电流电极和耦合到第三电力轨的第二电流电极。

公开(公告)号：US08951863B2

公开(公告)日：2015-02-10

申请号：US13780591

申请日：2013-02-28

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L27/115 ,  H01L21/82 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L21/82 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。

公开(公告)号：US20140295639A1

公开(公告)日：2014-10-02

申请号：US14301900

申请日：2014-06-11

申请人： FENG ZHOU ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： FENG ZHOU ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L45/00

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇层（911,1211） 。

公开(公告)号：US08779405B2

公开(公告)日：2014-07-15

申请号：US13486690

申请日：2012-06-01

申请人： Feng Zhou ,  Frank K. Baker, Jr. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： Feng Zhou ,  Frank K. Baker, Jr. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L29/02

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211） 。