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    Etching device
    24.
    发明授权
    Etching device 失效
    蚀刻装置

    公开(公告)号：US5376214A

    公开(公告)日：1994-12-27

    申请号：US118203

    申请日：1993-09-09

    申请人： Yasukazu Iwasaki ,  Makoto Uchiyama

    发明人： Yasukazu Iwasaki ,  Makoto Uchiyama

    IPC分类号： C23F1/00 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/67086 ,  G01N21/31 ,  H01L21/30604 ,  H01L21/67075 ,  H01L21/67253 ,  G01N21/76

    摘要： An etching device performing an etching process on a material immersed in a etchant which is a mixture of acids of which the main components are fluoric acid, nitric acid, and acetic acid. The etching device includes a semiconductor electrode immersed in the etchant, an opposing electrode immersed in the etchant, an electron meter for detecting an electric potential difference between the semiconductor electrode and the opposing electrode, and a controller for uniformly controlling the nitrite ion concentration in the etchant from the electric potential difference between the semiconductor electrode and the opposing electrode, detected by the electronmeter.

    摘要翻译： 对浸渍在蚀刻剂中的材料进行蚀刻处理的蚀刻装置，所述蚀刻剂是主要成分是酸，硝酸和乙酸的酸的混合物。 蚀刻装置包括浸没在蚀刻剂中的半导体电极，浸在蚀刻剂中的相对电极，用于检测半导体电极和对置电极之间的电位差的电子计量器，以及用于均匀地控制半导体电极和相对电极中的亚硝酸根离子浓度的控制器 由电子计检测的半导体电极和对置电极之间的电位差的蚀刻剂。

    Process for etching semiconductors using a hydrazine and metal hydroxide-containing etching solution
    26.
    发明授权
    Process for etching semiconductors using a hydrazine and metal hydroxide-containing etching solution 失效
    使用肼和含金属氢氧化物的蚀刻溶液蚀刻半导体的方法

    公开(公告)号：US5804090A

    公开(公告)日：1998-09-08

    申请号：US617215

    申请日：1996-03-18

    申请人： Yasukazu Iwasaki ,  Norihiko Kiritani ,  Makiko Mitamura ,  Takatoshi Noguchi ,  Makoto Uchiyama

    发明人： Yasukazu Iwasaki ,  Norihiko Kiritani ,  Makiko Mitamura ,  Takatoshi Noguchi ,  Makoto Uchiyama

    IPC分类号： G01L9/00 ,  G01P15/08 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/30608 ,  G01L9/0042 ,  G01P15/0802

    摘要： An etching process for a silicon semiconductor substrate to produce a semiconductor pressure sensor or a semiconductor acceleration sensor. The etching process comprises the following steps: (a) carrying out an etching of the semiconductor without application of a voltage to the semiconductor so as to accomplish a pre-etching step, the pre-etching step including dipping the semiconductor in hydrazine hydrate; and (b) carrying out an electrochemical etching of the semiconductor by applying pre-etching step so as to accomplish a final etching step, the final etching step including dipping the semiconductor in an alkali system etching solution containing at least hydrazine (N.sub.2 H.sub.4), potassium hydroxide (KOH), and water (H.sub.2 O), the alkali system etching solution containing potassium hydroxide in an amount of not less than 0.3% by weight.

    摘要翻译： 一种硅半导体衬底的蚀刻工艺，用于制造半导体压力传感器或半导体加速度传感器。 蚀刻工艺包括以下步骤：（a）对半导体进行不施加电压的蚀刻，以实现预蚀刻步骤，所述预蚀刻步骤包括将半导体浸入水合肼中; 并且（b）通过施加预蚀刻步骤进行半导体的电化学蚀刻，以便完成最终的蚀刻步骤，最后的蚀刻步骤包括将半导体浸入至少含有肼（N 2 H 4），钾 氢氧化物（KOH）和水（H 2 O），含有不小于0.3重量％的氢氧化钾的碱系蚀刻溶液。

    Electrochemical process and system for etching semiconductor substrates
    27.
    发明授权
    Electrochemical process and system for etching semiconductor substrates 失效
    用于蚀刻半导体衬底的电化学工艺和系统

    公开(公告)号：US5681448A

    公开(公告)日：1997-10-28

    申请号：US578920

    申请日：1995-12-27

    申请人： Makoto Uchiyama ,  Hidetoshi Nojiri ,  Yasukazu Iwasaki

    发明人： Makoto Uchiyama ,  Hidetoshi Nojiri ,  Yasukazu Iwasaki

    IPC分类号： C25F3/12 ,  C25F7/00

    CPC分类号： C25F3/12 ,  C25F7/00

    摘要： An electrochemical etching process carried out in an etching system including an electrolysis vessel which is provided thereinside with facing wall surfaces defining therebetween an etching solution flow region. A semiconductor substrate to be etched and a counter electrode are mounted respectively on the facing wall surfaces. A flow stream generating section for the etching solution is formed separate from the etching solution flow region and includes a device for generating the flow stream of the etching solution. The flow stream generating section is connected to the etching solution flow region in such a manner that the etching solution flow in a direction generally parallel with the facing wall surfaces inside the electrolysis vessel. An electric potential is applied between the semiconductor substrate and the counter electrode to accomplish an electrochemical etching on the semiconductor substrate.

    摘要翻译： 在包括电解容器的蚀刻系统中执行的电化学蚀刻工艺，其中设置有电解槽，其中在其间限定有蚀刻溶液流动区域。 要蚀刻的半导体衬底和对电极分别安装在相对的壁表面上。 用于蚀刻溶液的流动流产生部分与蚀刻溶液流动区域分离形成，并且包括用于产生蚀刻溶液的流动流的装置。 流动流产生部分以蚀刻溶液流动方向大致平行于电解容器内的相对的壁表面的方式连接到蚀刻液流动区域。 在半导体衬底和对电极之间施加电位以在半导体衬底上实现电化学蚀刻。

    Semiconductor device with leakage current prevention
    28.
    发明授权
    Semiconductor device with leakage current prevention 失效
    具有防漏电流的半导体器件

    公开(公告)号：US5614753A

    公开(公告)日：1997-03-25

    申请号：US575904

    申请日：1995-12-20

    申请人： Susumu Uchikoshi ,  Shigeyuki Kiyota ,  Yasukazu Iwasaki ,  Takatoshi Noguchi ,  Makoto Uchiyama

    发明人： Susumu Uchikoshi ,  Shigeyuki Kiyota ,  Yasukazu Iwasaki ,  Takatoshi Noguchi ,  Makoto Uchiyama

    IPC分类号： H01L21/822 ,  G01P15/08 ,  H01L27/04 ,  H01L29/82

    CPC分类号： G01P15/0802

    摘要： A semiconductor device is produced through electrolytic etching process. The device comprises a P-type silicon substrate. An N-type epitaxial layer is formed on the silicon substrate. P-type regions are defined in the N-type epitaxial layer. N-type regions are defined in some of the P-type regions. A first wiring layer connects to predetermined ones of the P-type regions. A second wiring layer connects to predetermined ones of the N-type regions. The semiconductor device has a given part which has such a possibility that a predetermined magnitude of leakage current flows therethrough between the first and second wiring layers when subjected to the electrolytic etching process. The semiconductor device further has a circuit which is electrically connected to one of the first and second wiring layers. The circuit is capable of removing the possibility of the leakage current flow through the given part when opened.

    摘要翻译： 通过电解蚀刻工艺制造半导体器件。 该器件包括P型硅衬底。 在硅衬底上形成N型外延层。 P型区域被限定在N型外延层中。 在一些P型区域中定义了N型区域。 第一布线层连接到预定的P型区域。 第二布线层连接到预定的N型区域。 半导体器件具有给定的部分，其具有在进行电解蚀刻处理时在第一和第二布线层之间流过预定大小的漏电流的可能性。 半导体器件还具有电连接到第一和第二布线层之一的电路。 该电路能够消除打开时泄漏电流流经给定部件的可能性。

    Semiconductor wafer to be etched electrochemically
    29.
    发明授权
    Semiconductor wafer to be etched electrochemically 失效
    要电化学蚀刻的半导体晶片

    公开(公告)号：US5172207A

    公开(公告)日：1992-12-15

    申请号：US747582

    申请日：1991-08-20

    申请人： Hidetoshi Nojiri ,  Makoto Uchiyama

    发明人： Hidetoshi Nojiri ,  Makoto Uchiyama

    IPC分类号： C25F3/30 ,  H01L21/306 ,  H01L21/3063

    CPC分类号： H01L21/3063

    摘要： A semiconductor wafer including a plurality of chips having respective portions to be etched electrochemically with application of an electric voltage to the semiconductor wafer immersed in an etching solution. The semiconductor wafer includes electric circuits formed therein for controlling electric energy applied to the respective portions.

    摘要翻译： 一种半导体晶片，其包括多个芯片，其具有将要浸入蚀刻溶液中的半导体晶片施加电压的电化学蚀刻的各部分。 半导体晶片包括形成在其中的用于控制施加到各个部分的电能的电路。

    Electrochemical etching method
    30.
    发明授权
    Electrochemical etching method 失效
    电化学蚀刻法

    公开(公告)号：US5167778A

    公开(公告)日：1992-12-01

    申请号：US740521

    申请日：1991-08-05

    申请人： Hiroyuki Kaneko ,  Makoto Uchiyama ,  Hidetoshi Nojiri ,  Norihiko Kiritani

    发明人： Hiroyuki Kaneko ,  Makoto Uchiyama ,  Hidetoshi Nojiri ,  Norihiko Kiritani

    IPC分类号： G01L9/04 ,  C25F3/30 ,  G01L9/00 ,  H01L21/3063 ,  H01L29/84

    CPC分类号： H01L21/3063

    摘要： An electrochemical etching method for producing semiconductor diaphragms from a semiconductor wafer comprised of a first semiconductor layer of a first conductivity type and a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a second conductivity type different than the first semiconductor layer. The semiconductor wafer is placed in an etching solution with respect to a counter-electrode immersed in the etching solution. The semiconductor wafer has a plurality of chips each of which includes at least one third semiconductor layer of the first conductivity type. The third semiconductor layer extends through the second semiconductor layer to the first semiconductor layer. A first positive potential is applied to the first and third semiconductor layers with respect to the counter-electrode. A second positive potential is applied to the second semiconductor layer with respect to the first semiconductor layer.

    摘要翻译： 一种用于从由第一导电类型的第一半导体层和形成在第一半导体层上形成的第二半导体层的半导体晶片制造半导体膜片的电化学蚀刻方法，所述第二半导体层具有不同于第一半导体层的第二导电类型 。 将半导体晶片相对于浸在蚀刻溶液中的对电极放置在蚀刻溶液中。 半导体晶片具有多个芯片，每个芯片包括至少一个第一导电类型的第三半导体层。 第三半导体层延伸穿过第二半导体层到第一半导体层。 第一和第三半导体层相对于反电极施加第一正电位。 第二正电位相对于第一半导体层施加到第二半导体层。