公开(公告)号：US10600649B2

公开(公告)日：2020-03-24

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US10586846B2

公开(公告)日：2020-03-10

申请号：US16010531

申请日：2018-06-18

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/20 ,  H01L21/266 ,  H01L29/78

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US10541338B2

公开(公告)日：2020-01-21

申请号：US16060549

申请日：2015-12-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  James Jay McMahon

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/167

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

公开(公告)号：US10014388B1

公开(公告)日：2018-07-03

申请号：US15398489

申请日：2017-01-04

Applicant: General Electric Company

Inventor： Victor Mario Torres ,  Reza Ghandi ,  David Alan Lilienfeld ,  Avinash Srikrishnan Kashyap ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/74 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/861 ,  H01L29/78

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

公开(公告)号：US09704949B1

公开(公告)日：2017-07-11

申请号：US15199262

申请日：2016-06-30

Applicant: General Electric Company

Inventor： Reza Ghandi ,  Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/872 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/872

Abstract: A charge-balanced (CB) diode may include one or more CB layers. Each CB layer may include an epitaxial layer having a first conductivity type and a plurality of buried regions having a second conductivity type. Additionally, the CB diode may include an upper epitaxial layer having the first conductivity type that is disposed adjacent to an uppermost CB layer of the one or more CB layers. The upper epitaxial layer may also include a plurality of junction barrier (JBS) implanted regions having the second conductivity type. Further, the CB diode may include a Schottky contact disposed adjacent to the upper epitaxial layer and the plurality of JBS implanted regions.