公开(公告)号：US20160284643A1

公开(公告)日：2016-09-29

申请号：US14865589

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Jagar SINGH ,  Ashish BARASKAR ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112 ,  H01L23/528 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

Abstract translation: 提出了具有纳米线熔断体的半导体熔丝及其制造方法。 所述方法包括例如：制造半导体熔丝，所述半导体熔丝包括至少一个纳米线熔断体，所述制造包括：形成至少一个纳米线，所述至少一个纳米线包括半导体材料; 并且使所述至少一个纳米线与金属反应以形成所述半导体熔丝的所述至少一个纳米线熔断体，所述至少一个纳米线熔断体包括半导体 - 金属合金。 在另一方面，提出了一种结构。 所述结构包括：半导体熔丝，所述半导体熔丝包括：至少一个纳米线熔断体，所述至少一个纳米线熔断体包括半导体 - 金属合金。

公开(公告)号：US20160071835A1

公开(公告)日：2016-03-10

申请号：US14477390

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Amaury GENDRON-HANSEN ,  Jagar SINGH ,  Andy WEI

IPC: H01L27/02 ,  H01L21/285 ,  H01L29/45 ,  H01L29/423 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L21/28568 ,  H01L27/0255 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66356 ,  H01L29/7391

Abstract: A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.

Abstract translation: 提供一种形成金属栅极二极管ESD保护器件的方法和所得到的器件。 实施例包括在基板上形成包括金属栅极的金属栅极二极管; 在所述金属栅极二极管的第一侧上形成n型阴极; 以及在所述金属栅极二极管的与所述第一侧相对的第二侧上形成p型阳极。

公开(公告)号：US20160056231A1

公开(公告)日：2016-02-25

申请号：US14467420

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH

IPC: H01L29/06 ,  H01L29/735 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/735

Abstract: Semiconductor devices and fabrication methods thereof are provided. The semiconductor devices include: a substrate, the substrate including a p-type well adjoining an n-type well; a first p-type region and a first n-type region disposed within the n-type well of the substrate, where the first p-type region at least partially encircles the first n-type region; and a second p-type region and a second n-type region disposed in the p-type well of the substrate, where the second n-type region at least partially encircles the second p-type region. In one embodiment, the first p-type region fully encircles the first n-type region and the second n-type region fully encircles the second p-type region. In another embodiment, the semiconductor device may be a bipolar junction transistor or a rectifier.

Abstract translation: 提供半导体器件及其制造方法。 所述半导体器件包括：衬底，所述衬底包括邻接n型阱的p型阱; 第一p型区域和第一n型区域，其设置在衬底的n型阱内，其中第一p型区域至少部分地环绕第一n型区域; 以及设置在所述基板的p型阱中的第二p型区域和第二n型区域，其中所述第二n型区域至少部分地环绕所述第二p型区域。 在一个实施例中，第一p型区域完全环绕第一n型区域，而第二n型区域完全环绕第二p型区域。 在另一个实施例中，半导体器件可以是双极结型晶体管或整流器。

公开(公告)号：US20150035053A1

公开(公告)日：2015-02-05

申请号：US13958938

申请日：2013-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7835

Abstract: Semiconductor devices and methods for manufacturing an LDMOS FinFET integrated circuit. The intermediate semiconductor device includes a substrate, a first well in the substrate, a second well in the substrate, and at least two polysilicon gates. The first well overlaps the second well and the at least one first gate is disposed over the first well and at least one second gate is disposed over the second well. The method includes forming a channel region and a drift region in the substrate, wherein the channel region overlaps the drift region, forming a shallow trench isolation region in the drift region, forming at least one first gate over the channel region, forming at least one second gate over the shallow trench isolation region, and applying at least one metal layer over the at least one first gate and the at least one second gate.

Abstract translation: 用于制造LDMOS FinFET集成电路的半导体器件和方法。 中间半导体器件包括衬底，衬底中的第一阱，衬底中的第二阱以及至少两个多晶硅栅极。 第一阱与第二阱重叠，并且至少一个第一栅极设置在第一阱上，并且至少一个第二栅极设置在第二阱上。 该方法包括在衬底中形成沟道区域和漂移区域，其中沟道区域与漂移区域重叠，在漂移区域中形成浅沟槽隔离区域，在沟道区域上形成至少一个第一栅极，形成至少一个 在浅沟槽隔离区域上的第二栅极，以及在所述至少一个第一栅极和所述至少一个第二栅极上施加至少一个金属层。