公开(公告)号：US20160322298A1

公开(公告)日：2016-11-03

申请号：US15207652

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Andy WEI ,  Sudharshanan RAGHUNATHAN

IPC: H01L23/528 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

Abstract translation: 在Mx线之前光刻地切割Mx线的方法通过图案化光刻定义，并且提供所得到的2DSAV器件。 实施例包括在SiO 2层上形成a-Si虚拟金属层; 在所述a-Si虚拟金属层上形成第一软掩模堆叠; 将通过第一软掩模堆叠的多个通孔图形化成SiO 2层; 移除第一软掩模层; 在a-Si虚拟金属层上形成第一和第二蚀刻停止层，形成在多个通孔中的第一蚀刻停止层; 在第二蚀刻停止层上形成a-Si心轴; 在每个a-Si心轴的相对侧上形成氧化物间隔物; 去除a-Si心轴; 在氧化物间隔物下面的a-Si虚拟金属层中形成a-Si虚拟金属线; 并在a-Si虚拟金属线之间形成SiOC层。

公开(公告)号：US20160020277A1

公开(公告)日：2016-01-21

申请号：US14871289

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L27/02

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US20150214330A1

公开(公告)日：2015-07-30

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jin Ping LIU ,  Guillaume BOUCHE ,  Andy WEI ,  Lakshmanan H. VANAMURTHY ,  Cuiqin XU ,  Sridhar KUCHIBHATLA ,  Rama KAMBHAMPATI ,  Xiuyu CAI

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US20160071835A1

公开(公告)日：2016-03-10

申请号：US14477390

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Amaury GENDRON-HANSEN ,  Jagar SINGH ,  Andy WEI

IPC: H01L27/02 ,  H01L21/285 ,  H01L29/45 ,  H01L29/423 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L21/28568 ,  H01L27/0255 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66356 ,  H01L29/7391

Abstract: A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.

Abstract translation: 提供一种形成金属栅极二极管ESD保护器件的方法和所得到的器件。 实施例包括在基板上形成包括金属栅极的金属栅极二极管; 在所述金属栅极二极管的第一侧上形成n型阴极; 以及在所述金属栅极二极管的与所述第一侧相对的第二侧上形成p型阳极。

公开(公告)号：US20150255353A1

公开(公告)日：2015-09-10

申请号：US14197267

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Jinping LIU ,  Xiang HU ,  Dae-han CHOI ,  Dae Geun YANG ,  Churamani GAIRE ,  Akshey SEHGAL

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L27/0924

Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.

Abstract translation: 公开了用单个掩模版形成FinFET源极/漏极区域的方法以及所得到的器件。 实施例可以包括在衬底上形成第一鳍片和第二鳍片，形成跨越第一鳍片和第二鳍片的栅极，在栅极的两侧去除第一鳍片和第二鳍片的部分，在第二鳍片上形成硅磷顶部 第一鳍片和第二鳍片代替部分，去除第一鳍片上的磷磷顶部，并且在第一鳍片上形成硅锗顶部代替硅磷顶部。

公开(公告)号：US20170309560A1

公开(公告)日：2017-10-26

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Jason Eugene STEPHENS ,  Tuhin GUHA NEOGI ,  Kai SUN ,  Deniz Elizabeth CIVAY ,  David Charles PRITCHARD ,  Andy WEI

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/5226

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20160329278A1

公开(公告)日：2016-11-10

申请号：US15134435

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Andy WEI ,  Sudharshanan RAGHUNATHAN

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

Abstract translation: 提供了在形成后续金属层之前形成2D自对准通孔并降低所得器件和所得器件的电容的方法。 实施例包括在SiOC层中形成虚拟金属线并沿第一方向延伸; 用金属线替代虚拟金属线，每条金属线都有氮化物盖; 在氮化物盖和SiOC层上形成软掩模堆叠; 通过所述软掩模堆叠将多个通孔图形化成金属线，所述多个通孔沿着第二方向自对准; 去除软掩码堆栈; 在金属线上形成第二虚拟金属线并在第二方向上延伸; 在SiOC层上的虚拟第二金属线之间形成第二SiOC层; 并且用第二金属线代替虚拟第二金属线，第二金属线通过通孔与金属线电连接。

公开(公告)号：US20160064372A1

公开(公告)日：2016-03-03

申请号：US14469155

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN ,  Manjunatha PRABHU ,  Anil KUMAR

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

公开(公告)号：US20160020204A1

公开(公告)日：2016-01-21

申请号：US14871181

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN

IPC: H01L27/02 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US20150325473A1

公开(公告)日：2015-11-12

申请号：US14275448

申请日：2014-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kisik CHOI ,  Hoon KIM ,  Andy WEI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

Abstract translation: 提供了用金属 - 氧化钛触点形成半导体器件的器件和方法。 一个中间半导体器件包括例如：衬底，设置在衬底上的至少一个场效应晶体管，位于至少一个场效应晶体管的至少第一部分之间的第一接触区域，位于间隔物和中间层之间 电介质和位于至少一个场效应晶体管的至少一个第二部分之间的第二接触区域在间隔物和层间电介质之间。 一种方法包括例如获得中间半导体器件并在中间半导体器件上形成至少一个接触。