公开(公告)号：US12040388B2

公开(公告)日：2024-07-16

申请号：US17525634

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Alexander Derrickson

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/6625

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

公开(公告)号：US11949004B2

公开(公告)日：2024-04-02

申请号：US17533882

申请日：2021-11-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Alexander M. Derrickson

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7393 ,  H01L29/0649 ,  H01L29/66325

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

公开(公告)号：US11843044B2

公开(公告)日：2023-12-12

申请号：US17578687

申请日：2022-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

公开(公告)号：US11837653B2

公开(公告)日：2023-12-05

申请号：US17555561

申请日：2021-12-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alvin J. Joseph ,  Andreas Knorr ,  Judson R. Holt

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/737 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

公开(公告)号：US11810969B2

公开(公告)日：2023-11-07

申请号：US17509384

申请日：2021-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20230098557A1

公开(公告)日：2023-03-30

申请号：US17578687

申请日：2022-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

公开(公告)号：US20230083044A1

公开(公告)日：2023-03-16

申请号：US17457325

申请日：2021-12-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander M. Derrickson ,  John L. Lemon ,  Haiting Wang ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.

公开(公告)号：US20230067948A1

公开(公告)日：2023-03-02

申请号：US17540339

申请日：2021-12-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt

IPC: H01L29/739 ,  H01L29/66

Abstract: Structures for a diode and methods of fabricating a structure for a diode. The structure includes a layer comprised of a semiconductor material. The layer includes a first section, a second section, and a third section laterally positioned between the first section and the second section. The structure includes a first terminal having a raised semiconductor layer on the first section of the layer, a second terminal including a portion on the second section of the layer, and a gate on the third section of the layer.

公开(公告)号：US20220196909A1

公开(公告)日：2022-06-23

申请号：US17131997

申请日：2020-12-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Yusheng Bian ,  Dali Shao

IPC: G02B6/122 ,  G02B6/12 ,  H01L29/06

Abstract: Disclosed is a silicon-on-insulator (SOI) chip structure with a substrate-embedded optical waveguide. Also disclosed is a method for forming the SOI chip structure. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to a wafer bonding process that results in the SOI structure. Subsequently, front-end-of-the-line (FEOL) processing can be performed to form additional optical devices and/or electronic devices in and/or above the silicon layer. By embedding an optical waveguide within the substrate prior to wafer bonding as opposed to forming it during FEOL processing, strict limitations on the dimensions of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large such that the cut-off wavelength can be relatively long. Thus, such a substrate-embedded optical waveguide brings different functionality to the SOI chip structure as compared to FEOL optical waveguides.

公开(公告)号：US11217685B2

公开(公告)日：2022-01-04

申请号：US16909376

申请日：2020-06-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Herbert Ho ,  Vibhor Jain ,  John J. Pekarik ,  Claude Ortolland ,  Judson R. Holt ,  Qizhi Liu ,  Viorel Ontalus

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.