公开(公告)号：US4380371A

公开(公告)日：1983-04-19

申请号：US130780

申请日：1980-03-17

Applicant: Gene A. Frantz

Inventor： Gene A. Frantz

IPC: G02F1/1343 ,  G06F3/147 ,  G09G3/18 ,  G02F1/13

CPC classification number: G09G3/18 ,  G02F1/134327 ,  G06F3/147

Abstract: A plurality of character forming segments are affixed to one surface of a front and back plate of a liquid crystal device. Three conductors affixed to one of the plates are each coupled to approximately one-third of the segment electrodes affixed to that plate. A plurality of conductors are affixed to the other plate and are each coupled to three of the segment electrodes affixed to that plate. Liquid crystal material is disposed between the two plates. By making use of the display device and a disclosed keyboard scanning circuit, an eight character position liquid crystal display device and a keyboard may be coupled to an electronic calculator chip disposed in a standard twenty-eight pin package.

Abstract translation: 多个字符形成段固定在液晶装置的前板和后板的一个表面上。 固定在其中一个板上的三个导体各自耦合到固定到该板上的大约三分之一的段电极。 多个导体固定到另一个板上，并且各自连接到固定到该板上的三个段电极。 液晶材料设置在两个板之间。 通过利用显示装置和所公开的键盘扫描电路，可以将八字符位置的液晶显示装置和键盘耦合到设置在标准二十八个引脚封装中的电子计算器芯片。

公开(公告)号：US4357489A

公开(公告)日：1982-11-02

申请号：US118138

申请日：1980-02-04

Applicant: Alva E. Henderson ,  Gene A. Frantz

Inventor： Alva E. Henderson ,  Gene A. Frantz

IPC: G09B19/06 ,  G10L13/04 ,  G10L1/00

CPC classification number: G09B19/06 ,  G10L13/047

Abstract: Integrated circuit speech synthesis system utilizing complementary metal-insulator-semiconductor technology to achieve low voltage operation, wherein a pluse width modulated digital-to-analog converter is employed to provide for accurate conversion of digital signals into analog signals even though the low voltage operation prohibits the large voltage swings normally required for digital-to-analog converter circuitry. The speech synthesis system includes a linear predictive filter as a speech synthesizer which utilizes coded reflection coefficients to produce digital signals representative of human speech. A microprocessor controls the access of digitized speech data which is stored in a memory. The speech synthesizer and microprocessor along with the pulse width modulated digital-to-analog converter are implemented in complementary metal-insulator-semiconductor technology. The system also includes a speaker for generating audible sounds in the form of synthesized human speech from the analog signals provided by the digital-to-analog converter.

Abstract translation: 利用互补金属绝缘体半导体技术实现低电压操作的集成电路语音合成系统，其中采用宽度调制的数模转换器来提供数字信号到模拟信号的精确转换，即使低电压操作禁止 数模转换器电路通常需要大的电压摆幅。 语音合成系统包括作为语音合成器的线性预测滤波器，其利用编码反射系数来产生表示人类语音的数字信号。 微处理器控制存储在存储器中的数字化语音数据的访问。 语音合成器和微处理器以及脉冲宽度调制的数模转换器在互补金属绝缘体半导体技术中实现。 该系统还包括一个扬声器，用于根据由数模转换器提供的模拟信号，以合成的人类语音的形式产生可听见的声音。

公开(公告)号：US20080243636A1

公开(公告)日：2008-10-02

申请号：US11691926

申请日：2007-03-27

Applicant: Gene A. Frantz

Inventor： Gene A. Frantz

IPC: G06F17/00

CPC classification number: G06Q30/02 ,  G06Q30/0601

Abstract: Embodiments of the invention to provide methods to provide on demand product placement to web based content. A method of in accordance with an embodiment of includes obtaining agreement between entities for placing a product in content. The products image or region of interest in the content is manipulated such that the product is emphasized; and content provider obtains payment for the content based activity of the content.

Abstract translation: 本发明的实施例提供了将按需产品放置到基于网络的内容的方法。 根据实施例的方法包括获得将产品置于内容中的实体之间的协议。 操作内容中的产品图像或感兴趣区域，使得产品被强调; 并且内容提供商获得对内容的基于内容的活动的支付。

公开(公告)号：US06904264B1

公开(公告)日：2005-06-07

申请号：US09713736

申请日：2000-11-15

Applicant: Gene A. Frantz

Inventor： Gene A. Frantz

IPC: H04H60/17 ,  H04H60/21 ,  H04H60/27 ,  H04H1/00

CPC classification number: H04H60/21 ,  H04H60/17 ,  H04H60/27 ,  H04H2201/183 ,  H04H2201/20 ,  H04H2201/30 ,  H04H2201/37 ,  H04H2201/50

Abstract: The user receives a digital radio transmission through a digital receiver and transmits a request to download selected content from this transmission to a content agent, an entity responsible for authorizing the authorized downloading of the digital content. If the content is not free of charge, the user also transmits sufficient information to allow for payment for the digital. The user then receives a transmission authorizing the downloading of the digital content from the content agent upon acceptance of the payment by the content agent. The user then downloads the content to a storage device which is coupled to the receiver.

Abstract translation: 用户通过数字接收机接收数字无线电传输，并将从该传输中下载所选内容的请求发送给负责授权下载数字内容的内容代理。 如果内容不是免费的，则用户还发送足够的信息以允许数字付款。 然后，用户在接受内容代理的支付时接收授权从内容代理下载数字内容的传输。 然后，用户将内容下载到耦合到接收器的存储设备。

公开(公告)号：US06662291B2

公开(公告)日：2003-12-09

申请号：US10190017

申请日：2002-07-05

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06418078B2

公开(公告)日：2002-07-09

申请号：US09745892

申请日：2000-12-21

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5680368A

公开(公告)日：1997-10-21

申请号：US473586

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和提供地址存储器阵列（24）的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5680358A

公开(公告)日：1997-10-21

申请号：US480636

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36), which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含地址缓冲寄存器（36），其存储随机存取地址和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5636176A

公开(公告)日：1997-06-03

申请号：US362289

申请日：1994-12-22

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John V. Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John V. Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disabled. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）被禁用。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5587962A

公开(公告)日：1996-12-24

申请号：US483003

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John V. Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John V. Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  H04B7/185 ,  G11C8/04

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。