公开(公告)号：US08484596B1

公开(公告)日：2013-07-09

申请号：US13614424

申请日：2012-09-13

申请人： Doris Tzu Lang Chen ,  Deshanand Singh

发明人： Doris Tzu Lang Chen ,  Deshanand Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A method for designing a system on a target device is disclosed. Extraction is performed on a first version of the system during synthesis in a first compilation resulting in a first netlist. Optimizations are performed on the first version of the system during synthesis in the first compilation resulting in a second netlist. Placement and routing are performed on the first version of the system in the first compilation. Extraction is performed on a second version of the system having a changed portion during synthesis in a second compilation resulting in a third netlist. The first version of the system in the first netlist and the second version of the system in the third netlist are differentiated to identify identical regions, wherein at least one of the performing and differentiating is performed by a processor.

摘要翻译： 公开了一种在目标设备上设计系统的方法。 在第一次汇编中的合成期间，在系统的第一版本上执行提取，得到第一个网表。 在第一次编译中的合成期间，在系统的第一版本上执行优化，从而产生第二个网表。 在第一个编译中，系统的第一个版本执行放置和布线。 在合成中具有改变部分的系统的第二版本在第二编译中执行提取，得到第三网表。 区分第一网表中的系统的第一版本和第三网表中的系统的第二版本，以识别相同的区域，其中执行和区分中的至少一个由处理器执行。

公开(公告)号：US08650525B2

公开(公告)日：2014-02-11

申请号：US13531344

申请日：2012-06-22

申请人： Doris Tzu Lang Chen ,  Deshanand Singh

发明人： Doris Tzu Lang Chen ,  Deshanand Singh

IPC分类号： G06F17/50

CPC分类号： G06F8/48 ,  G06F17/5054 ,  G06F2217/86

摘要： Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.

摘要翻译： 提供了用于提高集成电路（IC）的可编程逻辑的编译过程的速度和降低处理能力的系统和方法。 例如，在一个实施例中，一种方法包括获得高级程序，包括用于在集成电路（IC）的可编程逻辑上实现的计算机可读指令; 将高级程序转换为代表执行高级程序的功能所需的功能组件的低级代码; 生成包括用于基于所述高级程序实现所述低级代码的计算机可读指令的主机程序; 获得对高级程序的修改; 确定所述修改是否可以通过利用所述低级代码的新的主机程序来实现; 并且当通过新的主机程序利用低级代码实现修改时，生成新的主机程序来实施修改。

公开(公告)号：US20130212365A1

公开(公告)日：2013-08-15

申请号：US13369829

申请日：2012-02-09

申请人： Doris Tzu-Lang Chen ,  Deshanand Singh

发明人： Doris Tzu-Lang Chen ,  Deshanand Singh

IPC分类号： G06F15/177 ,  H04L12/56

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/66 ,  G06F2217/78 ,  H03K19/17736 ,  H04L41/0806 ,  H04L49/35

摘要： A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

摘要翻译： 准备用于使用高级语言配置的可编程集成电路器件的方法包括从所述高级语言的描述中编译多个虚拟可编程器件。 该编译包括从所述可编程集成电路装置的可编程资源编译配置路由资源的配置，以及从所述可编程集成电路装置的可编程资源编译多个复杂功能块的配置。 机器可读数据存储介质可以用这种编译配置的库进行编码。 虚拟可编程设备可以包括失速信号网络，并且虚拟可编程设备的路由交换机可以包括失速信号输入和输出。

公开(公告)号：US08296695B1

公开(公告)日：2012-10-23

申请号：US12802673

申请日：2010-06-11

申请人： Doris Tzu Lang Chen ,  Deshanand Singh

发明人： Doris Tzu Lang Chen ,  Deshanand Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.

摘要翻译： 公开了一种在目标设备上设计系统的方法。 具有第一组功能不变边界（FIB）的第一网表在第一次编译中合成系统的第一版本之后执行提取之后产生。 一个或多个FIB在第一集合中的合成期间执行优化之后，从第一组中无效，导致具有第二组FIB的第二网表。 具有第三组FIB的第三网表在合成具有第二编译中的改变部分的系统的第二版本之后执行提取之后生成。 遍历与第一网表和第三网表到达FIB的匹配节点的连接，以识别与相同区域相关联的等效节点。 第三网表中的相同区域被来自第二网表的优化合成区域替换。

公开(公告)号：US08214701B1

公开(公告)日：2012-07-03

申请号：US12425958

申请日：2009-04-17

申请人： Shawn Malhotra ,  Deshanand Singh

发明人： Shawn Malhotra ,  Deshanand Singh

IPC分类号： G01R31/28

CPC分类号： G06F11/273 ,  G01R31/31705 ,  G06F11/3656

摘要： An integrated hardware and software debugging system debugs software running on a processor and debugs hardware blocks that perform operations separate from the processor. Cycle traces are recorded for hardware block operations and the data is presented to a user through the same interface used for software debugging. Where hardware blocks are implemented in configurable circuitry (such as an FPGA) from source code, hardware debugging is linked to the source code to simulate stepping through the source code.

摘要翻译： 集成的硬件和软件调试系统调试在处理器上运行的软件，并调试执行与处理器分开的操作的硬件块。 记录周期轨迹用于硬件块操作，并通过用于软件调试的相同接口将数据呈现给用户。 在源代码中，在可配置电路（例如FPGA）中实现硬件块的情况下，硬件调试与源代码相关联，以模拟逐步通过源代码。

公开(公告)号：US07191426B1

公开(公告)日：2007-03-13

申请号：US10931953

申请日：2004-09-01

申请人： Deshanand Singh ,  Stephen Brown ,  Kevin Chan

发明人： Deshanand Singh ,  Stephen Brown ,  Kevin Chan

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical design. A second design for the system is generated that includes a second netlist describing a second logical design. Changes made to the first design in the second design are identified. Placement is performed on the changes made to the first design on the second design.

摘要翻译： 利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括为系统生成包括描述第一逻辑设计的第一网表以及第一逻辑设计的布局和路由的系统的第一设计。 生成系统的第二设计，其包括描述第二逻辑设计的第二网表。 确定了第二个设计中对第一个设计所做的更改。 对第二次设计上对第一个设计所做的更改执行放置。

公开(公告)号：US07107477B1

公开(公告)日：2006-09-12

申请号：US10357040

申请日：2003-01-31

申请人： Deshanand Singh ,  Andrew Hall

发明人： Deshanand Singh ,  Andrew Hall

IPC分类号： G03F7/38

CPC分类号： G06F17/5054 ,  H03K5/15066 ,  H03K19/1774 ,  H03K2005/00286

摘要： A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.

摘要翻译： 可编程逻辑器件具有可编程相移电路。 移相电路用于产生一组偏斜时钟信号，用于调整在可编程逻辑器件中合成的电路中的器件元件的相对定时。 通过适当地调节器件元件的相对定时，有效地减小了电路关键路径长度，从而提高了电路频率性能。 提供算法来建立时钟偏移值，从而改善电路性能。 这些算法被并入计算机辅助设计工具中，以实现电路设计的自动优化。

公开(公告)号：US10599404B1

公开(公告)日：2020-03-24

申请号：US13486151

申请日：2012-06-01

申请人： David Neto ,  Deshanand Singh ,  Tomasz Czajkowski ,  John Stuart Freeman ,  Tian Yi David Han

发明人： David Neto ,  Deshanand Singh ,  Tomasz Czajkowski ,  John Stuart Freeman ,  Tian Yi David Han

IPC分类号： G06F9/45 ,  G06F8/41 ,  G06F8/40

摘要： A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.

公开(公告)号：US20130346953A1

公开(公告)日：2013-12-26

申请号：US13531353

申请日：2012-06-22

申请人： Doris Tzu Lang Chen ,  Deshanand Singh

发明人： Doris Tzu Lang Chen ,  Deshanand Singh

IPC分类号： G06F9/45

CPC分类号： G06F8/48 ,  G06F17/5054

摘要： Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.

摘要翻译： 提供了用于提高集成电路（IC）的可编程逻辑的编译过程的速度和降低处理能力的系统和方法。 例如，在一个实施例中，一种方法包括获得高级程序，包括用于在集成电路（IC）的可编程逻辑上实现的计算机可读指令; 将高级程序转换为代表执行高级程序的功能所需的功能组件的低级代码; 生成包括用于基于所述高级程序实现所述低级代码的计算机可读指令的主机程序; 获得对高级程序的修改; 确定所述修改是否可以通过利用所述低级代码的新的主机程序来实现; 并且当通过新的主机程序利用低级代码实现修改时，生成新的主机程序来实施修改。

公开(公告)号：US20130346925A1

公开(公告)日：2013-12-26

申请号：US13531344

申请日：2012-06-22

申请人： Doris Tzu Lang Chen ,  Deshanand Singh

发明人： Doris Tzu Lang Chen ,  Deshanand Singh

IPC分类号： G06F17/50

CPC分类号： G06F8/48 ,  G06F17/5054 ,  G06F2217/86

摘要： Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.

摘要翻译： 提供了用于提高集成电路（IC）的可编程逻辑的编译过程的速度和降低处理能力的系统和方法。 例如，在一个实施例中，一种方法包括获得高级程序，包括用于在集成电路（IC）的可编程逻辑上实现的计算机可读指令; 将高级程序转换为代表执行高级程序的功能所需的功能组件的低级代码; 生成包括用于基于所述高级程序实现所述低级代码的计算机可读指令的主机程序; 获得对高级程序的修改; 确定所述修改是否可以通过利用所述低级代码的新的主机程序来实现; 并且当通过新的主机程序利用低级代码实现修改时，生成新的主机程序来实施修改。