公开(公告)号：US20060184747A1

公开(公告)日：2006-08-17

申请号：US11056721

申请日：2005-02-11

申请人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Phillip Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Phillip Williams

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0851

摘要： A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency matcher” may shift the cycle speed to a lower speed upon receiving snoop addresses from the interconnect thereby slowing down the rate at which requests are transmitted to the dispatch pipelines. Each dispatch pipeline is coupled to a sliced cache directory and is configured to search the cache directory to determine if data at the received addresses is stored in the cache memory. As a result of slowing down the rate at which requests are transmitted to the dispatch pipelines and accessing the two sliced cache directories simultaneously, the bandwidth or throughput of the cache directory may be improved.

摘要翻译： 用于提高缓存目录的窥探带宽的缓存，系统和方法。 高速缓存目录可以分成两个较小的缓存目录，每个具有自己的侦听逻辑。 通过具有可以同时访问的两个缓存目录，带宽可以基本上加倍。 此外，当从互连接收到窥探地址时，“频率匹配器”可以将周期速度转移到较低速度，从而将请求发送到调度管线的速率减慢。 每个调度流水线被耦合到一个切片缓存目录，并被配置为搜索该高速缓存目录以确定该接收到的地址上的数据是否被存储在该高速缓冲存储器中。 作为将请求发送到调度管线的速度变慢并且同时访问两个分片缓存目录的结果，可以提高缓存目录的带宽或吞吐量。

公开(公告)号：US20060179253A1

公开(公告)日：2006-08-10

申请号：US11054841

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F2212/1016 ,  G06F2212/1048

摘要： A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to the partial responses provided by the plurality of snoopers. The plurality masters includes a winning master that issues a request for a particular memory block, and the plurality of snoopers includes a protecting snooper that, in response to receipt of the request, provides a partial response and protects a transfer of coherency ownership of the particular memory block to the winning master until expiration of a protection window extension following receipt from the response logic of a combined response for the request.

摘要翻译： 数据处理系统包括存储器系统，发出对存储器系统内的存储器块的访问请求的多个主器件，提供对由主器件发出的请求的部分响应的多个监视器以及产生针对请求的组合响应的响应逻辑 响应于由多个窥探者提供的部分响应。 多个主人包括发出对特定存储块的请求的获胜主，并且多个窥探者包括保护窥探者，其响应于该请求的接收而提供部分响应并保护特定存储块的一致性所有权的转移 记忆块到获胜主机，直到从请求的组合响应的响应逻辑接收到保护窗口扩展之后到期。

公开(公告)号：US20070294486A1

公开(公告)日：2007-12-20

申请号：US11847941

申请日：2007-08-30

申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

公开(公告)号：US20070226427A1

公开(公告)日：2007-09-27

申请号：US11388017

申请日：2006-03-23

申请人： Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探独占访问操作，专用访问请求指定与地址标签匹配的目标地址，并且指示发起独占访问操作的请求者的相对域位置，第一高速缓存存储器从第一数据更新相关性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。

公开(公告)号：US20070226426A1

公开(公告)日：2007-09-27

申请号：US11388016

申请日：2006-03-23

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination. At least the first and second partial responses are accumulated to obtain a combined response for the exclusive access request. The combined response includes an indication of whether or not a highest point of coherency and a memory controller of a home system memory for the target address reside within a same coherency domain. The first cache memory updates the coherency state field from the first coherency state to a second coherency state in response to the indication in the combined response.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括用于系统存储器的系统存储器控制器和具有第一高速缓冲存储器的第一处理单元。 第二相关域包括具有第二高速缓冲存储器的第二处理单元。 在第一缓存存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为第一相关性状态。 响应于窥探专用访问请求，指定与地址标签匹配的目标地址，第一高速缓存存储器至少部分地基于第一相关性状态向独占访问请求提供第一部分响应。 响应于窥探专用访问请求，存储器控制器至少部分地基于确定的结果来确定它是否对目标地址负责并且向独占访问请求提供第二部分响应。 至少第一和第二部分响应被累积以获得专用访问请求的组合响应。 组合响应包括关于目标地址的家庭系统存储器的最高点的一致性和存储器控制器是否位于相同的一致性域内的指示。 响应于组合响应中的指示，第一缓存存储器将相关性状态字段从第一相关性状态更新为第二相关性状态。

公开(公告)号：US20070204110A1

公开(公告)日：2007-08-30

申请号：US11364774

申请日：2006-02-28

申请人： Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping a data-invalid state update request, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and that a memory block associated with the address tag is likely cached within the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探数据无效状态更新请求，第一缓存存储器将相关性状态字段从第一数据无效一致性状态更新为指示地址标签有效的第二数据无效一致性状态，存储位置 不包含有效数据，并且与地址标签相关联的存储器块可能被缓存在第一个相干域内。

公开(公告)号：US20070180196A1

公开(公告)日：2007-08-02

申请号：US11342951

申请日：2006-01-30

申请人： Guy Guthrie ,  John Hollaway ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  John Hollaway ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0822 ,  G06F12/0804 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括存储器控制器，具有由目标地址标识的目标存储器块的相关系统存储器，以及指示目标存储器块是否被高速缓存在第一相干域之外的域指示符。 在操作期间，第一相干域接收向第一和第二相干域广播的刷新操作，其中刷新操作指定目标存储器块的目标地址。 第一个相干域还接收表示对刷新操作的系统范围响应的刷新操作的组合响应。 响应于在组合响应的第一相关域中的接收，确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。 响应于组合响应指示目标存储器块的高速缓存副本可能保留在数据处理系统中的确定，更新域指示符以指示目标存储器块被高速缓存在第一相干域之外。

公开(公告)号：US20060271744A1

公开(公告)日：2006-11-30

申请号：US11140821

申请日：2005-05-31

申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0833 ,  G06F2212/507

摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.

摘要翻译： 根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。 通过参考预测器预测性地选择后续操作的广播范围。

公开(公告)号：US20060179245A1

公开(公告)日：2006-08-10

申请号：US11055476

申请日：2005-02-10

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

公开(公告)号：US20060179244A1

公开(公告)日：2006-08-10

申请号：US11055418

申请日：2005-02-10

申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.

摘要翻译： 高速缓存一致数据处理系统至少包括支持第一处理单元的第一高速缓冲存储器和支持第二处理单元的第二高速缓冲存储器。 第一缓存存储器包括缓存阵列和高速缓存阵列的内容的高速缓存目录。 响应于第一高速缓冲存储器在互连上检测指定请求地址的广播操作，第一高速缓冲存储器从操作中确定与请求地址相关联的操作类型和一致性状态。 响应于确定类型和一致性状态，第一高速缓存存储器过滤掉广播操作而不访问高速缓存目录。