公开(公告)号：US06665231B2

公开(公告)日：2003-12-16

申请号：US10243664

申请日：2002-09-16

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，使用流水线动态存储器（PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK1），并且将刷新所需的访问设为未占用 时隙（从未发布任何外部访问请求的定时）在流水线动态存储器的流水线中。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。

公开(公告)号：US20070101088A1

公开(公告)日：2007-05-03

申请号：US11641808

申请日：2006-12-20

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F13/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

公开(公告)号：US07165151B2

公开(公告)日：2007-01-16

申请号：US11010324

申请日：2004-12-14

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/00 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

公开(公告)号：US07159067B2

公开(公告)日：2007-01-02

申请号：US10702482

申请日：2003-11-07

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

IPC分类号： G06F12/12 ,  G06F13/00

CPC分类号： G06F12/0607 ,  G06F12/0882

摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同组时，DRAM的存储区地址并通过INDEX字段和TAG字段的操作生成，以便INDEX在写入INDEX时保留的本地访问变化并访问 相同但TAG不同可以分配给不同的银行。 高速访问是可能的，因为可以将主存储器的访问分配给单独的存储区。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。

公开(公告)号：US06438641B1

公开(公告)日：2002-08-20

申请号：US09495954

申请日：2000-02-02

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

IPC分类号： G06F1212

CPC分类号： G06F12/0607 ,  G06F12/0882

摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同组时，DRAM的存储区地址并通过INDEX字段和TAG字段的操作生成，以便INDEX在写入INDEX时保留的本地访问变化并访问 相同但TAG不同可以分配给不同的银行。 高速访问是可能的，因为可以将主存储器的访问分配给单独的存储区。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。

公开(公告)号：US20050099876A1

公开(公告)日：2005-05-12

申请号：US11010324

申请日：2004-12-14

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4093 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

公开(公告)号：US06847578B2

公开(公告)日：2005-01-25

申请号：US10729934

申请日：2003-12-09

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

公开(公告)号：US06708249B2

公开(公告)日：2004-03-16

申请号：US10101063

申请日：2002-03-20

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

公开(公告)号：US06285626B1

公开(公告)日：2001-09-04

申请号：US09730785

申请日：2000-12-07

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C800

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

公开(公告)号：US06885593B2

公开(公告)日：2005-04-26

申请号：US10683441

申请日：2003-10-14

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，使用流水线动态存储器（PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK 1），并且进行刷新所需的访问 未被占用的时隙（从未发布任何外部访问请求的定时）在流水线动态存储器的流水线中。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。