公开(公告)号：US08199549B2

公开(公告)日：2012-06-12

申请号：US12859445

申请日：2010-08-19

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C5/06

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US07813156B2

公开(公告)日：2010-10-12

申请号：US12242164

申请日：2008-09-30

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C5/06

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。

公开(公告)号：US07254680B2

公开(公告)日：2007-08-07

申请号：US11641808

申请日：2006-12-20

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/00 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

公开(公告)号：US07106123B2

公开(公告)日：2006-09-12

申请号：US11117479

申请日：2005-04-29

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： H03L5/00

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

摘要翻译： 公开了一种包括电平转换器（LSC）的半导体器件。 电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2） 电源（VDDQ）。 升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。 该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。 为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC） 自动控制防泄漏，外接控制信号。

公开(公告)号：US20060146623A1

公开(公告)日：2006-07-06

申请号：US11363085

申请日：2006-02-28

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电 到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US20050190588A1

公开(公告)日：2005-09-01

申请号：US11118338

申请日：2005-05-02

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/22

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US06885593B2

公开(公告)日：2005-04-26

申请号：US10683441

申请日：2003-10-14

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，使用流水线动态存储器（PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK 1），并且进行刷新所需的访问 未被占用的时隙（从未发布任何外部访问请求的定时）在流水线动态存储器的流水线中。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。

公开(公告)号：US06715025B2

公开(公告)日：2004-03-30

申请号：US10186891

申请日：2002-07-02

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

IPC分类号： G06F1300

CPC分类号： G06F12/0607 ,  G06F12/0882

摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同库时，通过INDEX字段和TAG字段的操作来生成DRAM的存储区地址，以使其INDEX变化的本地访问在写入INDEX时被保留 相同但是TAG不同可以分配给不同的存储体，从而实现高速存取。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。

公开(公告)号：US06469948B2

公开(公告)日：2002-10-22

申请号：US09885066

申请日：2001-06-21

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory. (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，流水线动态存储器。 （PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK1），并且对未占用时隙进行刷新所需的访问（任何外部访问请求的定时 在流水线动态存储器的流水线中永远不会发布）。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。

公开(公告)号：US06381671B1

公开(公告)日：2002-04-30

申请号：US09342240

申请日：1999-06-29

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。