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    Method of forming a contact in semiconductor device
    22.
    发明授权
    Method of forming a contact in semiconductor device 有权
    在半导体器件中形成接触的方法

    公开(公告)号：US06271108B1

    公开(公告)日：2001-08-07

    申请号：US09313258

    申请日：1999-05-18

    申请人： Jeong-Dong Choe

    发明人： Jeong-Dong Choe

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897

    摘要： The present invention relates to a method of forming a contact in semiconductor device, more particularly, to a method of forming a borderless contact in semiconductor device which minimizes loss of field oxide on forming a contact hole, reducing leakage current at an interface between an active area and a field area and preventing another loss of silicon and silicide in the active area by forming a barrier layer on a field oxide layer for separating devices in order to enhance a process margin of forming the contact hole in the active area due to a reduced design rule and an increased device integrity. The present invention includes the steps of forming a trench on a semiconductor substrate wherein the trench defines an active area and a field area, filling up the trench with an insulating layer, forming a barrier layer just on the insulating layer, forming a transistor in the active layer wherein the transistor has an impurity diffusion region, forming an insulating interlayer on a surface of the substrate including the transistor and the barrier layer, and forming at least a contact hole by removing a predetermined portion of the insulating interlayer wherein the contact hole exposes both a portion of the impurity diffusion region and another portion of the barrier layer.

    摘要翻译： 本发明涉及一种在半导体器件中形成接触的方法，更具体地说，涉及一种在半导体器件中形成无边界接触的方法，该方法使形成接触孔的场氧化物的损耗最小化，减少了在活性物质之间的界面处的泄漏电流 区域和场区，并通过在用于分离器件的场氧化物层上形成阻挡层来防止有源区中的硅和硅化物的另一损失，以便增强由于减少了在有源区中形成接触孔的工艺余量 设计规则和增加的设备完整性。 本发明包括在半导体衬底上形成沟槽的步骤，其中沟槽限定有源区和场区，用绝缘层填充沟槽，在绝缘层上形成阻挡层，在绝缘层上形成晶体管 活性层，其中所述晶体管具有杂质扩散区，在包括所述晶体管和所述阻挡层的所述衬底的表面上形成绝缘中间层，并且通过去除所述绝缘中间层的预定部分形成至少接触孔，其中所述接触孔暴露 杂质扩散区域的一部分和势垒层的另一部分。

    Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
    23.
    发明授权
    Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same 有权
    具有增加的源/漏接触面积的垂直沟道鳍场效应晶体管及其制造方法

    公开(公告)号：US08466511B2

    公开(公告)日：2013-06-18

    申请号：US12613025

    申请日：2009-11-05

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78618

    摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    摘要翻译： 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

    Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems
    24.
    发明授权
    Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems 失效
    包括浮动栅极的非易失性半导体器件，其制造方法和相关系统

    公开(公告)号：US07902024B2

    公开(公告)日：2011-03-08

    申请号：US11896982

    申请日：2007-09-07

    申请人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    发明人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

    摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

    摘要翻译： 存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅 浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

    Methods of fabricating field effect transistors having multiple stacked channels
    25.
    发明授权
    Methods of fabricating field effect transistors having multiple stacked channels 有权
    制造具有多个堆叠通道的场效应晶体管的方法

    公开(公告)号：US07615429B2

    公开(公告)日：2009-11-10

    申请号：US11948175

    申请日：2007-11-30

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

    摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

    摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。 在预活化图案的相对端处，在衬底上形成源极/漏极区域。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

    METHODS OF FABRICATING FIELD EFFECT TRANSISTORS HAVING MULTIPLE STACKED CHANNELS
    27.
    发明申请
    METHODS OF FABRICATING FIELD EFFECT TRANSISTORS HAVING MULTIPLE STACKED CHANNELS 有权
    制作具有多个堆叠通道的场效应晶体管的方法

    公开(公告)号：US20080090362A1

    公开(公告)日：2008-04-17

    申请号：US11948175

    申请日：2007-11-30

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

    摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

    摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。 在预活化图案的相对端处，在衬底上形成源极/漏极区域。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

    Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same
    28.
    发明授权
    Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same 有权
    具有采用不对称掩埋绝缘层的两种不同操作模式的半导体器件及其制造方法

    公开(公告)号：US07214987B2

    公开(公告)日：2007-05-08

    申请号：US11011911

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L27/12 ,  H01L27/01

    CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

    摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

    摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。