公开(公告)号：US06791870B2

公开(公告)日：2004-09-14

申请号：US10418406

申请日：2003-04-18

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: G11C1100

CPC classification number: H01L27/222 ,  G11C11/16

Abstract: The invention includes a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit. The invention also includes methods of storing and retrieving information.

Abstract translation: 本发明包括具有存储器位堆栈的磁阻存储器件。 该堆叠包括在第一和第二磁性层之间的第一磁性层，第二磁性层和非磁性层。 第一导线靠近堆叠并被配置为用于从存储器位读取信息。 第一导线与第一或第二磁性层的欧姆连接。 第二导线与叠层隔开足够的距离，使得第二导线不被欧姆连接到堆叠，并被配置为用于将信息写入存储器位。 本发明还包括存储和检索信息的方法。

公开(公告)号：US06780653B2

公开(公告)日：2004-08-24

申请号：US10165352

申请日：2002-06-06

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L2100

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

公开(公告)号：US08592797B2

公开(公告)日：2013-11-26

申请号：US13591891

申请日：2012-08-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

公开(公告)号：US08354661B2

公开(公告)日：2013-01-15

申请号：US13166362

申请日：2011-06-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US20110303889A1

公开(公告)日：2011-12-15

申请号：US13166362

申请日：2011-06-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L27/26

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US07978491B2

公开(公告)日：2011-07-12

申请号：US12010651

申请日：2008-01-28

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US07932173B2

公开(公告)日：2011-04-26

申请号：US12121258

申请日：2008-05-15

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/00

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US07440339B2

公开(公告)日：2008-10-21

申请号：US11142448

申请日：2005-06-02

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/10

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个访问晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US07183621B2

公开(公告)日：2007-02-27

申请号：US10761247

申请日：2004-01-22

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L29/82 ,  G11C11/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

Abstract translation: 本发明提供一种形成MRAM单元的方法，该方法在制造期间使电短路的发生最小化。 沟槽中的第一导体设置在绝缘层中，并且绝缘层和第一导体的上表面被平坦化。 然后，电介质层被沉积成稍大于稍后形成的感应层的期望最终厚度的厚度。 然后对电介质层进行图案化和蚀刻，以形成第一导体上的电池形状的开口。 然后，将坡莫合金电镀在电池形状中以形成感测层。 感应层和电介质层被平坦化，然后沉积非磁性隧道势垒层。 最后，在隧道势垒层上方形成钉扎层。

公开(公告)号：US20060030144A1

公开(公告)日：2006-02-09

申请号：US11209025

申请日：2005-08-22

Applicant: Hasan Nejad ,  James Green

Inventor： Hasan Nejad ,  James Green

IPC: H01L21/4763

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.