公开(公告)号：US07387959B2

公开(公告)日：2008-06-17

申请号：US11209025

申请日：2005-08-22

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/00

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US07932173B2

公开(公告)日：2011-04-26

申请号：US12121258

申请日：2008-05-15

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/00

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US06933224B2

公开(公告)日：2005-08-23

申请号：US10402471

申请日：2003-03-28

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/302

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US08426305B2

公开(公告)日：2013-04-23

申请号：US13069005

申请日：2011-03-22

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/00

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US20110171825A1

公开(公告)日：2011-07-14

申请号：US13069005

申请日：2011-03-22

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US20080227289A1

公开(公告)日：2008-09-18

申请号：US12121258

申请日：2008-05-15

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/4763

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US20120319073A1

公开(公告)日：2012-12-20

申请号：US13591891

申请日：2012-08-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US07330367B2

公开(公告)日：2008-02-12

申请号：US11081652

申请日：2005-03-17

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C5/06

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US20060263979A1

公开(公告)日：2006-11-23

申请号：US11131994

申请日：2005-05-18

Applicant: Hasan Nejad ,  Gordon Haller ,  Thomas Figura ,  Ravi Iyer

Inventor： Hasan Nejad ,  Gordon Haller ,  Thomas Figura ,  Ravi Iyer

IPC: H01L21/8242 ,  H01L21/22 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302 ,  H01L21/38

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L27/10897 ,  Y10S439/917

Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.

Abstract translation: 本发明包括形成与半导体结构相关的器件的方法。 在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

公开(公告)号：US07042749B2

公开(公告)日：2006-05-09

申请号：US10438344

申请日：2003-05-15

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2213/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.