摘要:
A phase locked loop (PLL) circuit is disclosed comprising a phase detector for generating a phase error between an input oscillating signal and an output oscillating signal. A fractional frequency synthesizer (FFS) generates the output oscillating signal in response to the phase error, wherein the FFS comprises an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr. The variable I is an integer value, and the variable Fr is a fractional value, both of which are generated in response to the phase error.
摘要:
A computer system is disclosed comprising a host connected to a disk drive, the disk drive comprising a disk surface having a plurality of tracks arranged in an embedded servo format including servo track segments for storing servo data and data track segments for storing user data. The disk drive includes a read element operative during a user-data read operation for reading data from the disk surface to produce a time-multiplexed analog read signal that during a revolution of the disk represents analog read servo data during each of a first set of time intervals and represents analog read user data during each of a second set of time intervals. The disk drive includes a sampled signal processing circuit that generates a servo state variable while processing the time-multiplexed read signal during the first servo time interval and a user data state variable while processing the time-multiplexed read signal during the first user data time interval. The disk drive includes a servo state variable trap register for storing the servo state variable at the end of the first servo time interval. The disk drive includes a data state variable trap register for storing the user data state variable at the end of the first user data time interval. The disk drive includes a control circuit for providing the stored servo state variable to the sampled signal processing circuit at the beginning of the second servo time interval. The control circuit provides the stored user data state variable to the sampled signal processing circuit at the beginning of the second user data time interval.
摘要:
A disk drive includes a disk having a disk surface. The disk surface has a plurality of tracks arranged in an embedded servo format including servo track segments for storing servo data and data track segments for storing user data. Data from the disk surface is read to produce a time-multiplexed analog read signal that during a revolution of the disk represents analog read servo data during each of a first set of time intervals and represents analog read user data during each of a second set of time intervals. The disk drive further includes a controller and a channel integrated circuit chip. The controller includes a controller port. The channel integrated circuit chip includes an input for receiving the time-multiplexed analog read signal. The time-multiplexed analog read signal is processed to generate data symbols representing recovered servo data and recovered user data. The channel integrated circuit chip includes a channel port for transferring both the recovered servo data and the recovered user data. The disk drive further includes a communication bus connected between the channel port and the controller port. The channel port transfers both the recovered servo data and the recovered user data to the communication bus. The communication bus transfers both the recovered servo data and the recovered user data to the controller port.
摘要:
A system for polling a preamplifier unit to remotely determine pre-established parametric values in a disk drive is disclosed. The disk drive comprises a controller, a preamplifier, and a plurality of transducers. The system for polling the preamplifier comprises means in the controller for generating a succession of serial bit characters each representative of a different pattern. A means is provided for successively transferring said serial bit characters from the controller to the preamplifier unit. A plurality of individual bit lines are provided in the preamplifier unit representative of at least one parametric value. A means is included in the preamplifier unit for comparing each serial bit pattern character received with said plurality of individual bit lines, and for generating a match signal when a serial bit pattern character received matches the plurality of individual bit lines. A means is provided for transferring the match signal from the preamplifier unit to the controller.
摘要:
A disk drive comprising a plurality of read/write transducers, a programmable preamplifier, and a controller for furnishing control and data signals to the programmable preamplifier and for receiving data signals therefrom, is disclosed. The programmable preamplifier comprising a write data input circuit for receiving data signals to be supplied to a transducer, a read data output circuit for manifesting data signals supplied to said preamplifier unit by a transducer, and a transducer interface circuit for providing write data signals to a transducer and receiving read data signals from a transducer. The programmable preamplifier further comprises a multiplexer comprising a first multiplexer input connected to receive a first internal digital signal, a second multiplexer input connected to receive a second internal digital signal, a control input connected to receive a control signal for selecting between the first and second internal digital signals, and a multiplexer output for outputting the selected first or second internal digital signal. The multiplexer output is connected to an output terminal of the programmable preamplifier. The programmable preamplifier comprises a serial interface circuit for receiving serially presented control signals from the associated controller, including the control signal for selecting between the first and second internal digital signals.
摘要:
A gate generator useful for validating readout signals incorporates three channels, including differentiators and threshold comparators, and a logic circuit coupled to the output circuits of the channels for passing valid readout signals. The output signals of the comparators and of detected zero crossings derived from a differentiated signal are fed to the logic circuit for processing.
摘要:
An oscillator utilizing a pair of transistors interconnected with a resonance circuit in the collector circuits thereof such that by regulation of the current flow to the connected emitters, the frequency of oscillation is regulated.