公开(公告)号：US5124589A

公开(公告)日：1992-06-23

申请号：US691615

申请日：1991-04-25

申请人： Toru Shiomi ,  Shigeki Ohbayashi ,  Atsushi Ohba

发明人： Toru Shiomi ,  Shigeki Ohbayashi ,  Atsushi Ohba

IPC分类号： G11C11/414 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

摘要翻译： 自定时随机存取存储器件包括可随机访问的存储器电路（7），响应外部时钟信号产生内部时钟信号的时钟发生器（9），响应于内部时钟信号的输入电路（8'） 用于锁存和输出所提供的输入信号;响应于内部时钟信号的输出电路（11'），用于锁存和输出来自存储器件的输出;以及电路（81,82,85,86; 115,116,124， 响应于用于禁止输入电路和输出电路的锁存功能的通过状态指定信号（TH，THM）的控制信号（125; 135,136,144,145）。 可以响应于通过状态指定信号，在与外部提供的时钟信号同步操作的模式和与外部提供的时钟信号异步操作的另一模式之间切换存储​​器件。

公开(公告)号：US08743645B2

公开(公告)日：2014-06-03

申请号：US13325945

申请日：2011-12-14

申请人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

摘要： In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

摘要翻译： 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。

公开(公告)号：US20120087198A1

公开(公告)日：2012-04-12

申请号：US13325945

申请日：2011-12-14

申请人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

摘要翻译： 针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。 该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。 电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。 在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。 因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

公开(公告)号：US20070030741A1

公开(公告)日：2007-02-08

申请号：US11492031

申请日：2006-07-25

申请人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

摘要翻译： 针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。 该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。 电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。 在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。 因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

公开(公告)号：US06301678B1

公开(公告)日：2001-10-09

申请号：US09167713

申请日：1998-10-07

申请人： Hirotoshi Sato ,  Tomohisa Wada ,  Shigeki Ohbayashi

发明人： Hirotoshi Sato ,  Tomohisa Wada ,  Shigeki Ohbayashi

IPC分类号： G11C2900

CPC分类号： G11C29/48

摘要： In a semiconductor memory device having a plurality of data input/output pins, control pins (e.g. address pins and external control signal pins) are arranged parallel to each other on a chip. The plurality of data input/output pins are divided into a plurality of groups. Each group has a specific data input/output pin. The specific data input/output pin is lined up with the control pins. In a test mode, a signal is written into all memory cells by applying the signal to the specific data input/output pin. In addition, whether the signals read from all memory cells are correct or not is determined using the specific data input/output pin.

摘要翻译： 在具有多个数据输入/输出引脚的半导体存储器件中，控制引脚（例如地址引脚和外部控制信号引脚）在芯片上彼此平行布置。 多个数据输入/输出引脚被分成多个组。 每组有一个特定的数据输入/输出引脚。 具体的数据输入/输出引脚与控制引脚对齐。 在测试模式下，通过将信号施加到特定数据输入/输出引脚，将信号写入所有存储单元。 此外，使用特定数据输入/输出引脚确定从所有存储单元读取的信号是否正确。

公开(公告)号：US5734281A

公开(公告)日：1998-03-31

申请号：US731992

申请日：1996-10-23

申请人： Chikayoshi Morishima ,  Shigeki Ohbayashi

发明人： Chikayoshi Morishima ,  Shigeki Ohbayashi

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/22

CPC分类号： G11C5/147

摘要： A small-sized semiconductor integrated circuit is provided in which the potential of a predetermined node can be set to an intermediate potential in a short period after a power source is turned on. By using a power on reset signal which is inverted when a source potential is set to a predetermined intermediate potential, a P channel MOS transistor whose source directly receives the source potential supplies charges to the predetermined node at an early stage after the power source is turned on until the source potential reaches the intermediate potential.

摘要翻译： 提供一种小型半导体集成电路，其中在电源接通之后，可以在短时间内将预定节点的电位设置为中间电位。 通过使用当电源电位被设定为预定的中间电位时反相的上电复位信号，源极直接接收源极电位的P沟道MOS晶体管在电源被切换之后的早期阶段向预定的节点供电 直到源电位达到中间电位。

公开(公告)号：US5666324A

公开(公告)日：1997-09-09

申请号：US616386

申请日：1996-03-15

申请人： Ryuichi Kosugi ,  Shigeki Ohbayashi

发明人： Ryuichi Kosugi ,  Shigeki Ohbayashi

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A synchronous semiconductor memory device includes a clock pulse generator generating internal first and second clock pulses in synchronization with an external clock signal for application, respectively, to a word line select decoder selecting a row of memory cells, and to a bit line select decoder selecting a column of memory cells, a sense amplifier sensing and amplifying a data of selected memory cell and a write driver writing a data to the selected memory cell. Word line select decoder is enabled when the first clock pulse is active, and bit line select decoder, sense amplifier and write driver are activated when the second clock pulse is active. These circuits are activated only for a necessary minimum period, and current consumption is reduced.

摘要翻译： 同步半导体存储器件包括时钟脉冲发生器，分别产生与应用的外部时钟信号同步的内部第一和第二时钟脉冲到选择一行存储器单元的字线选择解码器，以及位线选择解码器选择 一列存储单元，一个感测放大器，用于感测和放大所选存储单元的数据，以及一写入驱动器将数据写入所选存储单元。 当第一个时钟脉冲有效时，字线选择解码器被使能，当第二个时钟脉冲有效时，位线选择解码器，读出放大器和写入驱动器被激活。 这些电路仅在必要的最小周期被激活，并且电流消耗被降低。

公开(公告)号：US5544105A

公开(公告)日：1996-08-06

申请号：US271691

申请日：1994-07-07

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改进操作特性和可靠性的各种布置。

公开(公告)号：US20090268531A1

公开(公告)日：2009-10-29

申请号：US12457936

申请日：2009-06-25

申请人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C5/14

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

公开(公告)号：US07570525B2

公开(公告)日：2009-08-04

申请号：US11492031

申请日：2006-07-25

申请人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

摘要翻译： 针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。 该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。 电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。 在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。 因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。