公开(公告)号：US5515326A

公开(公告)日：1996-05-07

申请号：US402221

申请日：1995-03-10

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

公开(公告)号：US5764573A

公开(公告)日：1998-06-09

申请号：US787803

申请日：1997-01-23

申请人： Masayuki Iketani ,  Shigeki Ohbayashi

发明人： Masayuki Iketani ,  Shigeki Ohbayashi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/00 ,  G11C11/401 ,  G11C29/02 ,  H03K5/12 ,  G11C13/00

CPC分类号： G11C29/02 ,  G06F11/006

摘要： A checking circuit is provided which electrically and selectively connects a pad to which an internal circuit is connected, to a reference potential source node, in accordance with a potential of a special pad, when activated. The checking circuit is activated when a burn-in mode detection signal is activated. By detecting a leak current of a pin terminal to which the pad connected to the circuit is electrically connected, the potential of the special pad, that is, set internal function, can be externally identified. Accordingly, a bonding option function of which internal function is set in accordance with the potential of the bonding pad, can be externally detected in a non-destructive manner.

摘要翻译： 提供了一种检查电路，其在被激活时根据特殊焊盘的电位将选择性地连接内部电路的焊盘电连接到参考电位源节点。 当激活老化模式检测信号时，检查电路被激活。 通过检测连接到电路的焊盘电连接的引脚端子的泄漏电流，可以从外部识别专用焊盘的电位，即设置内部功能。 因此，可以以非破坏性的方式外部检测根据接合焊盘的电位设定内部功能的接合选择功能。

公开(公告)号：US5506805A

公开(公告)日：1996-04-09

申请号：US402212

申请日：1995-03-10

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

公开(公告)号：US06813202B2

公开(公告)日：2004-11-02

申请号：US10619476

申请日：2003-07-16

申请人： Masayuki Iketani

发明人： Masayuki Iketani

IPC分类号： G11C700

CPC分类号： G11C29/12005 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/41 ,  G11C29/50 ,  G11C29/50016

摘要： A semiconductor integrated circuit device includes a plurality of memory cells, a first voltage generating circuit for generating a first voltage, a second voltage generating circuit for generating a second voltage lower than the first voltage and a switching circuit for changing over the first and second voltages in response to a control signal so as to output the first and second voltages to the memory cells in a normal operation mode and a data retention test mode, respectively.

摘要翻译： 半导体集成电路器件包括多个存储器单元，用于产生第一电压的第一电压产生电路，用于产生低于第一电压的第二电压的第二电压产生电路和用于切换第一和第二电压的开关电路 响应于控制信号，以分别在正常操作模式和数据保持测试模式下将第一和第二电压输出到存储器单元。

公开(公告)号：US5544105A

公开(公告)日：1996-08-06

申请号：US271691

申请日：1994-07-07

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改进操作特性和可靠性的各种布置。

公开(公告)号：US5703510A

公开(公告)日：1997-12-30

申请号：US608075

申请日：1996-02-28

申请人： Masayuki Iketani ,  Shigeki Ohbayashi

发明人： Masayuki Iketani ,  Shigeki Ohbayashi

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power on reset circuit includes a transistor connected between a power supply node and a first node, a first capacitor connected between a ground node and a first node, a resistance element connected parallel to the first capacitor, a first CMOS inverter circuit having an input node connected to the first node and an output node connected to the second node, and a second CMOS inverter circuit having an input node connected to the second node and an output node connected to the first node. Preferably, the power on reset circuit further includes a second capacitor connected between the power supply node and the second node. In the power on reset circuit, when the power is turned off, the first capacitor is fully discharged by the resistance element. Therefore, a reset signal for initializing internal circuitry can be surely generated even when the power is again turned on.

摘要翻译： 上电复位电路包括连接在电源节点和第一节点之间的晶体管，连接在接地节点和第一节点之间的第一电容器，与第一电容器并联连接的电阻元件，具有输入端的第一CMOS反相器电路 连接到第一节点的节点和连接到第二节点的输出节点，以及具有连接到第二节点的输入节点和连接到第一节点的输出节点的第二CMOS反相器电路。 优选地，上电复位电路还包括连接在电源节点和第二节点之间的第二电容器。 在上电复位电路中，当电源关闭时，第一电容器被电阻元件完全放电。 因此，即使再次接通电源，也可以可靠地产生用于初始化内部电路的复位信号。

公开(公告)号：US5629900A

公开(公告)日：1997-05-13

申请号：US526247

申请日：1995-09-11

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

公开(公告)号：US5491655A

公开(公告)日：1996-02-13

申请号：US402218

申请日：1995-03-10

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A semiconductor memory device has a plurality of memory cells arranged in rows and columns, a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and connecting memory cells on a corresponding column, first and second read data lines, and a plurality of pairs of first and second bipolar transistor provided for respective pairs of first and second bit lines. Each first bipolar transistor is coupled to the first read data line and each second bipolar transistor is coupled to the second read data line and a plurality of first switching circuits transfer potentials of the first and second bit lines to respective bases of corresponding first and second bipolar transistors. A reference line transmits a non-selection level voltage and a plurality of second switching circuits, operating complementary to the corresponding first switching circuits, transfer the non-selection level voltage to bases of corresponding first and second bipolar transistors. Generator circuitry generates non-selection level voltage having (i) a potential level lower than or equal to a low level potential of a selected bit line in a data reading operation mode and (ii) a potential level higher than or equal to a high level potential of the selected bit line in an operation mode other than the data reading operation mode.

摘要翻译： 半导体存储器件具有排列成行和列的多个存储单元，对应于相应列而排列的多对互补的第一和第二位线，并将相应列上的存储单元，第一和第二读取数据线以及 多对成对的第一和第二双极晶体管被提供用于各对第一和第二位线。 每个第一双极晶体管耦合到第一读取数据线，并且每个第二双极晶体管耦合到第二读取数据线，并且多个第一开关电路将第一和第二位线的电位转移到相应的第一和第二双极的相应基极 晶体管。 参考线发送非选择电平电压和与对应的第一开关电路互补的多个第二开关电路，将非选择电平电压传送到对应的第一和第二双极晶体管的基极。 发电机电路产生非选择电平电压，其具有（i）在数据读取操作模式中低于或等于所选位线的低电平电位的电位电平，以及（ii）高于或等于高电平的电位电平 在除数据读取操作模式之外的操作模式中所选位线的电位。

公开(公告)号：US06229365B1

公开(公告)日：2001-05-08

申请号：US08982033

申请日：1997-12-01

申请人： Masayuki Iketani ,  Shigeki Ohbayashi

发明人： Masayuki Iketani ,  Shigeki Ohbayashi

IPC分类号： H03K512

CPC分类号： G11C7/1078 ,  H03K19/018585

摘要： At the last stage of a level converter that provides an internal signal to an internal signal output node, MOS transistors that are rendered conductive alternatively are provided as current source transistors. These additional MOS transistors are selectively rendered conductive according to the voltage level of, for example, a bonding pad. The charging/discharging current towards the internal node can be adjusted. Accordingly, the rising time and falling time of the internal signal can be constantly made equal. Thus an input/output circuit that can provide a signal at a proper timing even when the operating environment such as the system power supply voltage changes can be implemented.

摘要翻译： 在向内部信号输出节点提供内部信号的电平转换器的最后阶段，作为电流源晶体管提供替代导通的MOS晶体管。 这些附加MOS晶体管根据例如焊盘的电压电位有选择地导通。 可以调节朝向内部节点的充电/放电电流。 因此，内部信号的上升时间和下降时间可以恒定地相等。 因此，即使可以实现诸如系统电源电压变化的操作环境，也可以在适当的定时提供信号的输入/输出电路。

公开(公告)号：US5659513A

公开(公告)日：1997-08-19

申请号：US526245

申请日：1995-09-11

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G05F3/24

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。