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公开(公告)号：US6023431A
公开(公告)日：2000-02-08
申请号：US724851
申请日：1996-10-03
申请人： Douglas J. Cutter , Kurt D. Beigel , Fan Ho
发明人： Douglas J. Cutter , Kurt D. Beigel , Fan Ho
CPC分类号： G11C29/785 , G11C17/18 , G11C29/83
摘要： A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.
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22.发明授权
公开(公告)号：US5982656A
公开(公告)日：1999-11-09
申请号：US813767
申请日：1997-03-07
申请人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
发明人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
摘要： Method and apparatus are disclosed for checking the resistance of programmable circuits in an integrated circuit where each programmable circuit includes a programmable element, such as an antifuse. A precharged node is connected to the programmable element and the voltage at the node discharges based on the resistance of the programmable element. An output signal is produced whose binary value is based on the voltage at the node after a sufficient time has elapsed to allow the initial voltage to discharge based on the resistance of the programmable element.
摘要翻译： 公开了用于检查集成电路中的可编程电路的电阻的方法和装置，其中每个可编程电路包括诸如反熔丝的可编程元件。 预充电节点连接到可编程元件，并且节点处的电压基于可编程元件的电阻而放电。 产生输出信号，其二进制值基于经过足够时间之后的节点处的电压，以允许初始电压基于可编程元件的电阻放电。
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公开(公告)号：US5973978A
公开(公告)日：1999-10-26
申请号：US143229
申请日：1998-08-28
申请人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel
发明人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel
CPC分类号： G11C17/18
摘要： A programmable circuit in an integrated circuit provides a programmed signal, which is based on the state of a first node. An anti-fuse includes a first terminal coupled to the first node and a second terminal coupled to a programming bus. An anti-fuse programming pad is coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit. The state of the programmed signal can be used to replace a primary circuit element in the integrated circuit, such a row or column of memory cells in a memory integrated circuit, with a redundant circuit element.
摘要翻译： 集成电路中的可编程电路提供基于第一节点的状态的编程信号。 反熔丝包括耦合到第一节点的第一端子和耦合到编程总线的第二端子。 反熔丝编程焊盘耦合到第一编程总线，用于允许足够的电压将从外部到集成电路施加到第一编程总线的第一反熔丝短路。 编程信号的状态可以用于替换集成电路中的主电路元件，即存储器集成电路中的存储单元的一行或多列，具有冗余电路元件。
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公开(公告)号：US5847441A
公开(公告)日：1998-12-08
申请号：US644232
申请日：1996-05-10
申请人： Douglas J. Cutter , Kurt D. Beigel
发明人： Douglas J. Cutter , Kurt D. Beigel
IPC分类号： G11C17/16 , G11C17/18 , H01L27/105 , H01L29/40
CPC分类号： H01L27/105 , G11C17/16 , G11C17/18
摘要： An integrated semiconductor junction antifuse is formed from either adjacent regions of opposite doping types or spaced apart regions of similar doping type within a substrate. In its unblown state, the junction antifuse forms an open circuit that blocks current from flowing while in the blown state, the junction antifuse conducts current. The junction antifuse is blown by applying a breakdown voltage sufficient to overcome a semiconductor junction so that current flows across the reverse-biased semiconductor junction. As current flows across the reverse-biased junction, dopant migration forms a conductive path so that the junction antifuse no longer forms an open circuit.
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公开(公告)号：US08609492B2
公开(公告)日：2013-12-17
申请号：US13192207
申请日：2011-07-27
申请人： Kurt D. Beigel , Sanh D. Tang
发明人： Kurt D. Beigel , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L29/0638 , H01L27/1027 , H01L27/10802 , H01L29/0688 , H01L29/7841 , H01L29/78642 , H01L29/7889
摘要： Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.
摘要翻译： 提供了形成装置的方法以及与垂直存储单元相关联的装置。 形成垂直存储单元的一个示例性方法可以包括在导体线上形成半导体结构。 半导体结构可以具有包括第一和第二掺杂材料之间的第一结的第一区域。 在第一区域上方的半导体结构的第一对侧壁上形成蚀刻保护材料。 第一区域的体积相对于半导体结构的体区在第一维度上减小。
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公开(公告)号：US08035160B2
公开(公告)日：2011-10-11
申请号：US12627869
申请日：2009-11-30
IPC分类号： H01L29/66
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。
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公开(公告)号：US20100072532A1
公开(公告)日：2010-03-25
申请号：US12627869
申请日：2009-11-30
IPC分类号： H01L27/108 , H01L27/105
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。
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28.发明授权公开(公告)号：US07674683B2
公开(公告)日：2010-03-09
申请号：US12111014
申请日：2008-04-28
申请人： Kurt D. Beigel
发明人： Kurt D. Beigel
IPC分类号： H01L21/04 , H01L21/761
CPC分类号： H01L27/0814 , H01L27/0629 , H01L29/417 , H01L29/861
摘要： A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the doped region, and forming respective first and second polysilicon plugs within the first and second holes over the doped region. In one embodiment, the first and second polysilicon plugs are doped opposite one another such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, and has a cross-sectional area generally defined by the first or second hole adjacent the PN junction. Various devices, systems, and other methods are also disclosed.
摘要翻译： 公开了一种制造大容量隔离PN二极管的技术。 在一个实施例中，方法可以包括提供具有掺杂区域的衬底并且在掺杂区域上设置电介质材料。 该方法还可以包括在暴露掺杂区域的电介质材料中形成第一和第二孔，以及在掺杂区域上的第一和第二孔内形成相应的第一和第二多晶硅栓塞。 在一个实施例中，第一和第二多晶硅插塞彼此相对掺杂，使得PN结形成在第一或第二多晶硅插塞与衬底的掺杂区域之间，并且具有通常由第一或第二多晶硅 邻近PN结的第二个孔。 还公开了各种装置，系统和其它方法。
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公开(公告)号：US07645671B2
公开(公告)日：2010-01-12
申请号：US11598449
申请日：2006-11-13
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。
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公开(公告)号：US07384840B2
公开(公告)日：2008-06-10
申请号：US10930512
申请日：2004-08-31
申请人： Kurt D. Beigel
发明人： Kurt D. Beigel
IPC分类号： H01L21/8234
CPC分类号： H01L27/0814 , H01L27/0629 , H01L29/417 , H01L29/861
摘要： A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.
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