公开(公告)号：US06492270B1

公开(公告)日：2002-12-10

申请号：US09809832

申请日：2001-03-19

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76879

摘要： A different method is provided for forming high aspect ratio damascene structures with an integrated approach of combining electroless plating with physical vapor deposition of copper. A dual damascene structure, having a trench opening and a via opening, is first formed over a metal line on a substrate. The inside walls of the dual structure is lined with a diffusion barrier layer. Then, nitride spacers are formed on the inside walls of both the trench opening and the via opening. The via opening is further lined with a displacement, or, seed, layer. This is followed by forming electroless copper in the via opening, and hence a copper plug. A barrier metal is now formed over both the copper plug and the inside walls of the trench opening. Copper is next deposited over the barrier metal inside the trench, and including over the copper metal plug, using physical vapor deposition (PVD). Any excess metal is subsequently removed by CMP, thus forming a copper dual damascene interconnect that is highly conformable for high aspect ratios, and also void-free and reliable.

摘要翻译： 提供了一种用于形成高纵横比大马士革结构的不同方法，其结合无电镀与铜的物理气相沉积的综合方法。 首先在衬底上的金属线上形成具有沟槽开口和通孔开口的双镶嵌结构。 双重结构的内壁衬有扩散阻挡层。 然后，在沟槽开口和通孔开口的内壁上形成氮化物间隔物。 通孔开口进一步排列有位移或种子层。 接着在通路孔中形成化学镀铜，从而形成铜塞。 现在在铜塞和沟槽开口的内壁上形成阻挡金属。 接下来，铜沉积在沟槽内的阻挡金属上，并且使用物理气相沉积（PVD）包括在铜金属插塞上方。 随后通过CMP去除任何多余的金属，从而形成对于高纵横比高度适应的铜双镶嵌互连，并且无空隙和可靠。

公开(公告)号：US06358845B1

公开(公告)日：2002-03-19

申请号：US09808921

申请日：2001-03-16

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76837 ,  H01L21/76885

摘要： A method is disclosed for forming insulative inter metal dielectric (IMD) layers without the attendant problems of having voids, key-holes and air gaps. This is accomplished by reducing the aspect ratio of the gaps between metal lines through a judicious two-step dielectric filling process and through the use of two-step removal of the photoresist. That is, the gap is filled with photoresist first, and then partially removed, thereby leaving a portion in the gap to reduce the aspect ratio of the gap. When a second insulative layer is formed over the substrate, the gap between the metal lines is filled without the conventional attendant problem of forming voids or key-holes. Hence, void free IMD integration with improved IMD gap filling is achieved along with improved IMD thermal conductivity through the use of a metal liner.

摘要翻译： 公开了用于形成绝缘金属间介电层（IMD）层的方法，而不存在具有空隙，键孔和气隙的问题。 这是通过明智的两步介电填充工艺和通过使用两步除去光致抗蚀剂来减少金属线之间的间隙的纵横比来实现的。 也就是说，间隙首先用光致抗蚀剂填充，然后部分地去除，从而在间隙中留下一部分以减小间隙的纵横比。 当在基板上形成第二绝缘层时，填充金属线之间的间隙，而不会产生形成空隙或键孔的常规问题。 因此，通过使用金属衬垫，改善了IMD的导热性，实现了改进的IMD间隙填充的无空隙IMD整合。

公开(公告)号：US06245633B1

公开(公告)日：2001-06-12

申请号：US09454387

申请日：1999-12-03

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L2120

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L28/55 ,  Y10S438/964

摘要： A method for fabricating a stacked capacitor is described, which is applicable to the fabrication of a capacitor with a double-sided double crown bottom electrode. The first crown structure of the bottom electrode is established by forming a patterned material layer which comprises an opening on the substratae as the framework of the amorphous silicon layer of the bottom electrode. The second crown structure of the bottom electrode is to established on the above amorphous silicon layer by forming an amorphous silicon spacer on the sidewall of another patterned material layer.

摘要翻译： 描述了用于制造叠层电容器的方法，其可应用于制造具有双面双冠底电极的电容器。 底部电极的第一冠状结构通过形成图案化材料层而形成，该图案化材料层包括基底上的开口作为底部电极的非晶硅层的框架。 通过在另一个图案化材料层的侧壁上形成非晶硅间隔物，在上述非晶硅层上形成底部电极的第二冠状结构。

公开(公告)号：US06235579B1

公开(公告)日：2001-05-22

申请号：US09451384

申请日：1999-11-30

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L218242

CPC分类号： H01L21/7687 ,  H01L27/10852 ,  H01L28/60

摘要： A method of manufacturing a stacked capacitor. A first dielectric layer is formed over a substrate. A first nitride layer is formed on the first dielectric layer. A storage node contact hole is formed to penetrate through the first nitride layer and the first dielectric layer and to expose a portion of the substrate. A first conductive plug is formed in the storage node contact hole. A second dielectric layer is formed on the first nitride layer and the first conductive plug. A second nitride layer is formed on the second dielectric layer. A contact hole is formed to penetrate through the second nitride layer and the second dielectric layer and to expose portions of the first conductive plug. A second conductive plug is formed in the contact hole with a surface level lower than a surface level of the second nitride layer. A metal barrier layer is formed on the second conductive plug and fills the contact hole. A first metal layer is formed over the substrate. The first metal layer, the second nitride layer and the second dielectric layer are patterned to form a storage node. The storage node comprises the second conductive plug and the metal barrier layer. A metal spacer is formed on the sidewall of the storage node. A third dielectric layer is formed over the substrate. A second metal layer is formed on the third dielectric layer.

摘要翻译： 一种叠层电容器的制造方法。 第一电介质层形成在衬底上。 在第一电介质层上形成第一氮化物层。 存储节点接触孔形成为穿透第一氮化物层和第一电介质层并暴露衬底的一部分。 在存储节点接触孔中形成第一导电插塞。 在第一氮化物层和第一导电插塞上形成第二电介质层。 在第二电介质层上形成第二氮化物层。 形成接触孔以穿透第二氮化物层和第二电介质层并暴露第一导电插塞的部分。 第二导电插塞形成在接触孔中，其表面水平比第二氮化物层的表面水平低。 金属阻挡层形成在第二导电插塞上并填充接触孔。 第一金属层形成在衬底上。 对第一金属层，第二氮化物层和第二介质层进行图案化以形成存储节点。 存储节点包括第二导电插塞和金属阻挡层。 在存储节点的侧壁上形成金属间隔物。 第三电介质层形成在衬底上。 在第三电介质层上形成第二金属层。

公开(公告)号：US06218308B1

公开(公告)日：2001-04-17

申请号：US09314018

申请日：1999-05-19

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21311

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L28/55 ,  Y10S438/957

摘要： A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A polysilicon contact is then formed to fill into the contact hole. A metal layer is formed on the substrate and the polysilicon contact. Next, a silicon catching layer is formed on the metal layer. An annealing step is performed to substitute the silicon contact with a portion of said metal layer for forming a metal contact, wherein the silicon atom are driven to react with the silicon catching layer for forming a compound layer underneath the silicon catching layer. After the metal layer, the silicon catching layer and the compound layer are removed, the first conduction layer is formed on the substrate and the metal contact to serve as a bottom electrode. Then, a dielectric layer is formed along the surface of the first conduction layer. The second conduction layer is next formed on the dielectric layer to serve as a top electrode.

摘要翻译： 在本发明中提供了集成电路电容器的制造方法。 首先，蚀刻半导体衬底以形成接触孔。 然后形成多晶硅接触以填充到接触孔中。 在衬底和多晶硅接触上形成金属层。 接下来，在金属层上形成硅捕捉层。 执行退火步骤以将硅接触部与所述金属层的一部分取代以形成金属接触，其中驱动硅原子与硅捕获层反应以在硅捕获层下方形成化合物层。 在金属层之后，去除硅捕集层和化合物层，在基板和金属接触上形成第一导电层以用作底部电极。 然后，沿着第一导电层的表面形成电介质层。 接下来，在电介质层上形成第二导电层以用作顶部电极。

公开(公告)号：US06204141B1

公开(公告)日：2001-03-20

申请号：US09661098

申请日：2000-09-13

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21332

CPC分类号： H01L27/1087

摘要： A method of manufacturing a deep trench capacitor. A first silicon oxide layer is formed on a substrate. A first trench is formed in the substrate. A rugged polysilicon layer is formed on the surface of the first trench. The grains of the rugged polysilicon layer are distributed discretely on surface of the first trench. A second silicon oxide layer is formed on the rugged polysilicon layer. The exposed substrate in the first trench is etched, in order to form a plurality of second trenches in the substrate of the first trench. The first and second silicon oxide layer are removed. A first conductive layer is formed over the substrate and conformal to the first trench and the second trenches. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

摘要翻译： 一种制造深沟槽电容器的方法。 在基板上形成第一氧化硅层。 在衬底中形成第一沟槽。 在第一沟槽的表面上形成坚固的多晶硅层。 凹凸多晶硅层的晶粒离散地分布在第一沟槽的表面上。 在坚固的多晶硅层上形成第二氧化硅层。 蚀刻第一沟槽中的暴露的衬底，以在第一沟槽的衬底中形成多个第二沟槽。 去除第一和第二氧化硅层。 第一导电层形成在衬底上并与第一沟槽和第二沟槽保形。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。

公开(公告)号：US6162680A

公开(公告)日：2000-12-19

申请号：US317132

申请日：1999-05-24

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/87 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/91

摘要： The method for forming a capacitor in the present invention includes the steps as follows. At first, a multi-layer structure is formed on a semiconductor substrate, and the multi-layer structure is provided to have etching selectivity in etching neighboring layers in the multi-layer structure. A top dielectric layer is then formed on the multi-layer structure. A first opening is defined in the top dielectric layer, and a second opening is defined in the multi-layer structure under the first opening. Next, a wet etch is performed through the second opening to form at least two lateral openings in the multi-layer structure. Following the wet etch, a first conductive layer is formed conformably on the top dielectric layer, on sidewalls of the first opening and the second opening, and filled within the at least two lateral openings. A filling layer is then formed on the substrate, and the filling layer and the first conductive layer on the top dielectric layer are removed. The remained filling layer, the top dielectric layer, and the multi-layer structure are removed to leave a first electrode on the substrate. Finally, an inter-electrode dielectric layer is formed on the first electrode and a second conductive layer is formed on the inter-electrode dielectric layer to finish the formation of a capacitor.

摘要翻译： 在本发明中形成电容器的方法包括以下步骤。 首先，在半导体衬底上形成多层结构，并且提供多层结构以在多层结构中蚀刻相邻层的蚀刻选择性。 然后在多层结构上形成顶部电介质层。 第一开口限定在顶部电介质层中，并且在第一开口下的多层结构中限定第二开口。 接下来，通过第二开口进行湿蚀刻以在多层结构中形成至少两个侧向开口。 在湿蚀刻之后，第一导电层在第一开口和第二开口的侧壁上在顶部电介质层上顺应地形成，并且填充在至少两个侧向开口内。 然后在基板上形成填充层，并且去除顶部介电层上的填充层和第一导电层。 去除剩余的填充层，顶部电介质层和多层结构，以在衬底上留下第一电极。 最后，在第一电极上形成电极间电介质层，在电极间电介质层上形成第二导电层，结束电容器的形成。

公开(公告)号：US6100129A

公开(公告)日：2000-08-08

申请号：US189353

申请日：1998-11-09

申请人： Yeur-Luen Tu ,  Chine-Gie Lou

发明人： Yeur-Luen Tu ,  Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8244

CPC分类号： H01L28/82 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

摘要： A method for manufacturing a fin-trench capacitor is disclosed. The method comprises the steps of: forming a plurality of alternating oxide and nitride layers including a top oxide layer, wherein said nitride layers are sandwiched between said oxide layers; forming a storage node contact opening in said plurality of alternating oxide and nitride layers, stopping at said landing pad; removing a portion of said nitride layers along sidewalls of said contract opening; forming a polysilicon layer over said top oxide layer and conformally along said sidewalls of said contact opening; depositing a photoresist layer into said contact opening; removing a portion of said polysilicon layer on top of said top oxide layer; forming a dielectric layer over said top oxide layer and conformally on top of said polysilicon layer along said sidewalls of said contact opening; forming a top conductive layer over said dielectric layer and in said contact opening.

摘要翻译： 公开了一种用于制造鳍状沟槽电容器的方法。 该方法包括以下步骤：形成包括顶部氧化物层的多个交替的氧化物和氮化物层，其中所述氮化物层夹在所述氧化物层之间; 在所述多个交替的氧化物和氮化物层中形成存储节点接触开口，在所述着陆焊盘处停止; 沿着所述合约开口的侧壁去除所述氮化物层的一部分; 在所述顶部氧化物层上形成多晶硅层，并沿着所述接触开口的所述侧壁共形地形成多晶硅层; 将光致抗蚀剂层沉积到所述接触开口中; 在所述顶部氧化物层的顶部上去除所述多晶硅层的一部分; 在所述顶部氧化物层上形成电介质层，并沿着所述接触开口的所述侧壁保形地位于所述多晶硅层的顶部上; 在所述介​​电层上和所述接触开口中形成顶部导电层。

公开(公告)号：US06074913A

公开(公告)日：2000-06-13

申请号：US108901

申请日：1998-07-01

申请人： Chine-Gie Lou ,  Yeur-Luen Tu

发明人： Chine-Gie Lou ,  Yeur-Luen Tu

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/8242

CPC分类号： H01L28/92 ,  H01L21/28568 ,  H01L27/10852 ,  H01L28/84

摘要： A method for manufacturing a metal-insulator-metal capacitor on a substrate is disclosed. The method comprises the steps of: forming a first dielectric layer onto said substrate; patterning and etching said first dielectric layer to form a contact opening; forming a first metal layer onto said first dielectric layer and into said contact opening; forming a barrier layer onto said first metal layer; forming a second dielectric layer onto said barrier layer; forming a discrete HSG layer onto said second dielectric layer; etching said second dielectric layer by using said HSG layer as a mask; stripping said HSG layer; etching said barrier layer and said first metal layer by using a remaining portion of said second dielectric layer as a mask; stripping said remaining portion of said second dielectric layer; patterning and etching a remaining portion of said barrier layer and a remaining portion of said first metal layer; forming a third dielectric layer over said barrier layer, said first metal layer and said first dielectric layer; and forming a second metal layer over said third dielectric layer.

摘要翻译： 公开了一种在衬底上制造金属 - 绝缘体 - 金属电容器的方法。 该方法包括以下步骤：在所述衬底上形成第一电介质层; 图案化和蚀刻所述第一介电层以形成接触开口; 在所述第一介电层上形成第一金属层并进入所述接触开口; 在所述第一金属层上形成势垒层; 在所述阻挡层上形成第二电介质层; 在所述第二介电层上形成离散的HSG层; 通过使用所述HSG层作为掩模蚀刻所述第二介质层; 剥离HSG层; 通过使用所述第二介电层的剩余部分作为掩模蚀刻所述阻挡层和所述第一金属层; 剥离所述第二电介质层的剩余部分; 图案化和蚀刻所述阻挡层的剩余部分和所述第一金属层的剩余部分; 在所述阻挡层上形成第三电介质层，所述第一金属层和所述第一介电层; 以及在所述第三介电层上形成第二金属层。

公开(公告)号：US06856156B2

公开(公告)日：2005-02-15

申请号：US10400758

申请日：2003-03-26

申请人： Sheng-Hui Liang ,  Chine-Gie Lou

发明人： Sheng-Hui Liang ,  Chine-Gie Lou

IPC分类号： G01R1/073 ,  G01R31/02

CPC分类号： G01R1/07392

摘要： An automatically adjustable wafer probe card for the testing of integrated circuits fabricated on a wafer. The wafer probe card includes a pitch shift assembly having a shift block that includes a reserve needle block and an adjacent functional needle block. Multiple probe needles are linearly adjustable on the shift block, and a selected number of the probe needles can be shifted from the reserve needle block to the functional needle block depending on the number of contact pads on the integrated circuit to be contacted by the probe needles of the wafer probe card during the testing process. A selected spacing between the probe needles, or pitch, can be achieved by locating the probe needles at the selected spacings from each other along the functional needle block.

摘要翻译： 一种用于测试在晶圆上制造的集成电路的可自动调节的晶圆探针卡。 晶片探针卡包括具有移位块的俯仰移位组件，该移位块包括备用针块和相邻的功能性针座。 多个探针可以在移位块上线性调节，根据被探针接触的集成电路上的接触焊盘的数量，可将选定数量的探针从储备针头块移动到功能性针头块 的测试过程中的晶圆探针卡。 可以通过沿着功能性针块将探针定位在彼此间隔的选定间距来实现探针之间的间距或间距。