Thick Oxide P-Gate NMOS Capacitor for Use In A Low-Pass Filter of a Circuit and Method of Making Same
    21.
    发明申请
    Thick Oxide P-Gate NMOS Capacitor for Use In A Low-Pass Filter of a Circuit and Method of Making Same 失效
    用于电路的低通滤波器的厚氧化物P栅极NMOS电容器及其制造方法

    公开(公告)号:US20090253240A1

    公开(公告)日:2009-10-08

    申请号:US12484652

    申请日:2009-06-15

    IPC分类号: H01L21/02

    摘要: A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

    摘要翻译: 提出了具有介电厚度的电路,其包括包括具有厚栅极氧化物层的一个或多个半导体器件的低通滤波器,而该电路的另外的半导体器件具有薄的栅极氧化物层。 低通滤波器半导体器件包括N型衬底,形成在N型衬底上的P型区,在P型区上形成的厚栅氧化层,形成在厚栅极氧化物上的P +栅电极 并且耦合到第一电压供应线,以及P +拾取端子,其形成在与栅电极相邻的P型区域中并且耦合到第二电压供应线。 低通滤波器半导体器件用作电容器,由此栅极至衬底的电压保持在小于零伏特以保持电路的稳定的控制电压。

    Fine step and large gain range programmable gain amplifier
    22.
    发明申请
    Fine step and large gain range programmable gain amplifier 有权
    精细级和大增益范围可编程增益放大器

    公开(公告)号:US20050140451A1

    公开(公告)日:2005-06-30

    申请号:US10744785

    申请日:2003-12-24

    申请人: Derek Tam Ardie Venes

    发明人: Derek Tam Ardie Venes

    IPC分类号: H03G1/00 H03G3/10

    CPC分类号: H03G1/0088

    摘要: A programmable gain amplifier with three stages uses fine steps, has a large gain range, and is monotonic. The first stage comprises several amplifiers, each including a resistive feedback loop. The feedback loop comprises a series of resistors, with each resistor acting as a tap. Since the number of resistors in the loop is unchanging, monotonicity and stability is guaranteed when resistance is increased using successive taps. A switch system connects two taps at a time to an interpolation stage. Each of these taps corresponds to a specific resistor level, and thus a gain level. The interpolation stage uses a plurality of current sources inside a feedback amplifier to control the interpolation, in order to provide fine gain steps.

    摘要翻译: 具有三级的可编程增益放大器采用精细步长,增益范围大,是单调的。 第一级包括多个放大器,每个放大器包括电阻反馈回路。 反馈回路包括一系列电阻器,每个电阻器用作抽头。 由于环路中的电阻数量不变,当使用连续的抽头增加电阻时,保证单调性和稳定性。 开关系统一次将两个抽头连接到插补阶段。 这些抽头中的每一个对应于特定的电阻器电平,并因此对应于增益电平。 内插级在反馈放大器内部使用多个电流源来控制内插,以便提供精细的增益步骤。

    Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same
    23.
    发明申请
    Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same 有权
    用于电路的低通滤波器的厚氧化物P栅极NMOS电容器及其制造方法

    公开(公告)号:US20050087839A1

    公开(公告)日:2005-04-28

    申请号:US10975090

    申请日:2004-10-28

    摘要: A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

    摘要翻译: 提出了具有介电厚度的电路,其包括包括具有厚栅极氧化物层的一个或多个半导体器件的低通滤波器,而该电路的另外的半导体器件具有薄的栅极氧化物层。 低通滤波器半导体器件包括N型衬底,形成在N型衬底上的P型区,在P型区上形成的厚栅氧化层,P型区, 栅电极形成在厚栅极氧化物层上并耦合到第一电压供应线,以及形成在与栅电极相邻的P型区域中的P + +拾取端子,并耦合到第二电压源 线。 低通滤波器半导体器件用作电容器,由此栅极至衬底的电压保持在小于零伏特以保持电路的稳定的控制电压。

    Method And System For A Power Reduction Scheme For Ethernet PHYS
    24.
    发明申请
    Method And System For A Power Reduction Scheme For Ethernet PHYS 审中-公开
    用于以太网PHYS的功率降​​低方案的方法和系统

    公开(公告)号:US20130182717A1

    公开(公告)日:2013-07-18

    申请号:US13666901

    申请日:2012-11-01

    IPC分类号: H04L12/56

    CPC分类号: H04L12/66

    摘要: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

    摘要翻译: 提供了用于以太网PHY的功率降低方案的方法和系统的方面。 链路伙伴中的以太网PHY可以通过在无数据分组传输的非活动连接,10Base-T自动协商操作和/或活动10Base-T连接期间集成的发送DAC禁用传输。 DAC可以是电压模式或电流模式DAC。 PHY或MAC设备可以确定何时禁用经由DAC的传输。 在这方面,PHY或MAC设备可以产生用于禁止传输的适当信号。 当连接变为活动时或当有效的10Base-T连接准备好传输数据时,DAC可以被PHY或MAC设备启用。 此外,当以强制10Base-T操作模式操作时,PHY可以经由DAC进行传输,并且与链路伙伴的连接是活动的。

    METHOD AND SYSTEM FOR A POWER REDUCTION SCHEME FOR ETHERNET PHYS
    25.
    发明申请
    METHOD AND SYSTEM FOR A POWER REDUCTION SCHEME FOR ETHERNET PHYS 有权
    用于以太网的功率降低方案的方法和系统

    公开(公告)号:US20080253356A1

    公开(公告)日:2008-10-16

    申请号:US11734147

    申请日:2007-04-11

    IPC分类号: H04L12/66

    CPC分类号: H04L12/66

    摘要: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

    摘要翻译: 提供了用于以太网PHY的功率降低方案的方法和系统的方面。 链路伙伴中的以太网PHY可以通过在无数据分组传输的非活动连接,10Base-T自动协商操作和/或活动10Base-T连接期间集成的发送DAC禁用传输。 DAC可以是电压模式或电流模式DAC。 PHY或MAC设备可以确定何时禁用经由DAC的传输。 在这方面,PHY或MAC设备可以产生用于禁止传输的适当信号。 当连接变为活动时或当有效的10Base-T连接准备好传输数据时,DAC可以被PHY或MAC设备启用。 此外,当以强制10Base-T操作模式操作时,PHY可以经由DAC进行传输,并且与链路伙伴的连接是活动的。

    System and method for providing configurable, dynamic multimedia message service pre-transcoding
    26.
    发明申请
    System and method for providing configurable, dynamic multimedia message service pre-transcoding 审中-公开
    用于提供可配置的动态多媒体消息服务预转码的系统和方法

    公开(公告)号:US20070112978A1

    公开(公告)日:2007-05-17

    申请号:US11651053

    申请日:2007-01-09

    IPC分类号: G06F15/16

    CPC分类号: H04W4/18 H04W8/28

    摘要: System and methods for providing multimedia message service (MMS) interoperability between an initiating carrier and a destination carrier. A transcoding facility receives an MMS message from an initiating carrier and accesses a number portability database to determine an identity of a destination carrier to which the MMS message is intended to be sent and a carrier profile repository to obtain a carrier profile for the destination carrier, the carrier profile including information regarding an MMS format acceptable to the destination carrier. The transcoding facility determines, based on the carrier profile and a format of the MMS message received from the initiating carrier, whether the format of the MMS message received from the initiating carrier must be modified to be effectively received by the destination carrier and, if so, transcodes the MMS message in accordance with the carrier profile to generate a transcoded MMS message, and thereafter sends one of (i) the MMS message received from the initiating carrier and (ii) the transcoded MMS message to the destination carrier.

    摘要翻译: 用于在发起运营商和目的地运营商之间提供多媒体消息服务(MMS)互操作性的系统和方法。 代码转换设施从发起的载波接收MMS消息,并且访问号码便携性数据库以确定要发送MMS消息的目的地载波的标识,以及载波简档存储库,以获取目的地载波的载波简档, 载体简档包括关于目的地载波可接受的MMS格式的信息。 代码转换设备基于载波简档和从发起载波接收的MMS消息的格式来确定是否必须修改从起始载波接收的MMS消息的格式以便目的地载波有效地接收,如果是 根据载波简档对MMS消息进行转码,生成转码的MMS消息,然后发送(i)从发起载波接收的MMS消息和(ii)转码的MMS消息中的一个到目标载波。

    Intermediary content gateway system and method
    27.
    发明申请
    Intermediary content gateway system and method 有权
    中介内容网关系统及方法

    公开(公告)号:US20050201392A1

    公开(公告)日:2005-09-15

    申请号:US10852101

    申请日:2004-05-25

    IPC分类号: H04L12/28

    摘要: A system for enabling exchange of content over a communications network is disclosed having a first category of users comprising wireless carriers and a second category of users comprising content providers. A content gateway platform is provided having a database for storage of content. The content providers supply content to the database for use by the wireless carriers and the content is ultimately offered to end-user customers of the wireless carriers.

    摘要翻译: 公开了一种用于通过通信网络进行内容交换的系统,其具有包括无线运营商的第一类用户和包括内容提供商的第二类用户。 提供了具有用于存储内容的数据库的内容网关平台。 内容提供商向数据库提供内容以供无线运营商使用,并且内容最终被提供给无线运营商的最终用户客户。

    Programmable divider with built-in programmable delay chain for high-speed/low power application

    公开(公告)号:US06518805B2

    公开(公告)日:2003-02-11

    申请号:US09969135

    申请日:2001-10-03

    IPC分类号: H03K2100

    摘要: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

    System and method for billing augmentation
    29.
    发明申请
    System and method for billing augmentation 有权
    用于计费增加的系统和方法

    公开(公告)号:US20050216403A1

    公开(公告)日:2005-09-29

    申请号:US10837695

    申请日:2004-05-04

    IPC分类号: G06Q20/00 H04M15/00 G06F17/60

    摘要: System and method for providing augmented billing services. Where a billing system cannot keep pace with new services being marketed and the specialized pricing associated with such new services, a system and method are provided that generate a billing augmentation messages that are sent to the billing entity and that cause an incremental increase of a bill for the handling of a particular message type. The incremental increase is equivalent to a charge that the billing system is already configured to bill. In a preferred embodiment of the invention, the message is an electronic message such as an SMS message and the billing augmentation messages are generated by and sent from an intercarrier vendor.

    摘要翻译: 用于提供增强计费服务的系统和方法。 如果计费系统无法跟上正在上市的新服务和与这样的新服务相关联的专门定价,则提供一种系统和方法,其产生发送到计费实体的计费增加消息,并且导致账单的增量增加 用于处理特定的消息类型。 增量增加相当于计费系统已经配置为帐单的费用。 在本发明的优选实施例中,消息是诸如SMS消息的电子消息,并且计费增加消息由业务间供应商生成和发送。

    Apparatus for frequency dividing a master clock signal by a non-integer
    30.
    发明申请
    Apparatus for frequency dividing a master clock signal by a non-integer 有权
    用于将主时钟信号分频为非整数的装置

    公开(公告)号:US20050156639A1

    公开(公告)日:2005-07-21

    申请号:US11076137

    申请日:2005-03-10

    申请人: Ka Lun Choi Derek Tam

    发明人: Ka Lun Choi Derek Tam

    IPC分类号: H03K23/54 H03K21/00

    CPC分类号: H03K23/546

    摘要: A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

    摘要翻译: 分频电路将主时钟频率除以非整数因子以提供其频率等于主时钟信号的频率除以该非整数因子的输出时钟信号。 在一个实施例中,该电路用于将主时钟频率除以2.5。