公开(公告)号：US07001844B2

公开(公告)日：2006-02-21

申请号：US10835949

申请日：2004-04-30

申请人： Ashima B. Chakravarti ,  Shreesh Narasimha ,  Victor Chan ,  Judson Holt ,  Satya N. Chakravarti

发明人： Ashima B. Chakravarti ,  Shreesh Narasimha ,  Victor Chan ,  Judson Holt ,  Satya N. Chakravarti

IPC分类号： H01L21/469

CPC分类号： H01L21/0217 ,  C23C16/345 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3185 ,  H01L29/7843

摘要： Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.

公开(公告)号：US4300210A

公开(公告)日：1981-11-10

申请号：US108242

申请日：1979-12-27

申请人： Satya N. Chakravarti ,  Lawrence G. Heller ,  Wilbur D. Pricer

发明人： Satya N. Chakravarti ,  Lawrence G. Heller ,  Wilbur D. Pricer

IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/56 ,  G11C19/36 ,  H03K5/08 ,  G11C27/00 ,  G11C11/24 ,  G11C11/40

CPC分类号： G11C11/565 ,  G11C11/4091 ,  G11C19/36 ,  G11C7/06

摘要： A calibrated sensing system is provided in accordance with the teachings of this invention for sensing charge in a storage medium, such as a storage capacitor, coupled to an access or bit/sense line which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor or potential well and compared with the unknown charge in the first potential to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.

摘要翻译： 根据本发明的教导，提供了一种校准的感测系统，用于感测存储介质（例如存储电容器）中的电荷，该存储介质耦合到访问或位/检测线，其补偿存储介质中的大部分变异源，并且 接入线路。 在系统中，存储在存储介质中的未知电荷经由存取线路传送到第一电容器或势阱。 将存储介质的高电荷状态写入存储介质，并且从其准备已知的分数电荷分组，将其选择性地传输到第二电容器或势阱，并与第一电位中的未知电荷进行比较，以确定第 存储在存储介质中的未知电荷。 通过选择性地使用两个或更多个电荷多级感测的分数分组。

公开(公告)号：US4542340A

公开(公告)日：1985-09-17

申请号：US454900

申请日：1982-12-30

申请人： Satya N. Chakravarti ,  Paul L. Garbarino ,  Donald A. Miller

发明人： Satya N. Chakravarti ,  Paul L. Garbarino ,  Donald A. Miller

IPC分类号： H01L27/10 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108 ,  G01R31/26 ,  G01R31/00

CPC分类号： H01L27/108

摘要： A testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells; the testing structure includes two large gate-controlled diodes, each diode having a diffused junction which is substantially identical with that of the other diode, the gates of the diodes having different perimeter-to-area ratios, such that when testing is carried out, the leakage current components due to the contribution of the thin oxide area can be isolated from the perimeter-contributed components of the isolating thick oxide; dynamic testing can also be performed and, because of the small area for the test site, an "on chip" amplifier can be provided at the site.

摘要翻译： 用于制造动态RAM单元的漏电流表征的测试方法和结构; 测试结构包括两个大的栅极控制二极管，每个二极管具有与另一个二极管基本相同的扩散结，二极管的栅极具有不同的周长与面积比，使得当进行测试时， 由于薄氧化物区域的贡献导致的漏电流成分可以从隔离厚氧化物的周边贡献成分中分离出来; 也可以进行动态测试，由于测试点的面积小，可以在现场提供“片上”放大器。

公开(公告)号：US4287571A

公开(公告)日：1981-09-01

申请号：US74272

申请日：1979-09-11

申请人： Satya N. Chakravarti ,  John A. Hiltebeitel

发明人： Satya N. Chakravarti ,  John A. Hiltebeitel

IPC分类号： G11C17/00 ,  G11C5/02 ,  G11C17/08 ,  G11C17/12 ,  G11C17/16 ,  H01L21/8246 ,  H01L23/528 ,  H01L27/112 ,  H01L29/78 ,  G11C11/40

CPC分类号： G11C17/16 ,  G11C5/02 ,  H01L23/528 ,  H01L27/112 ,  H01L2924/0002

摘要： An array of transistors suitable for use in a read only memory includes a plurality of spaced apart first conductive lines insulated from a semiconductor substrate and a plurality of spaced apart second conductive lines insulated from the substrate and from the first lines and disposed to intersect the first lines. Diffusion regions formed in the substrate as current carrying electrodes are defined by the first and second lines. A plurality of spaced apart third conductive lines are arranged to intersect the first and second lines and to connect to the diffusion regions. When the array is used in a read only memory, selected transistors of the array are made to have a different threshold voltage than that of the remaining transistors and the first and second lines form word lines, the third lines form bit or sense and ground lines and the diffusion regions form the source and drain regions of the transistors, with each diffusion region serving up to four transistors or cells.

摘要翻译： 适用于只读存储器的晶体管阵列包括与半导体衬底绝缘的多个间隔开的第一导电线和与衬底和第一线绝缘的多个间隔开的第二导线，并且设置成与第一 线条。 作为载流电极形成在基板中的扩散区域由第一和第二线限定。 多个间隔开的第三导线布置成与第一和第二线相交并连接到扩散区。 当阵列用于只读存储器时，阵列的所选晶体管被制成具有与剩余晶体管不同的阈值电压，并且第一和第二线形成字线，第三线形成位或感测线和接地线 并且扩散区域形成晶体管的源极和漏极区域，其中每个扩散区域用作四个晶体管或单元。