公开(公告)号：US20050275375A1

公开(公告)日：2005-12-15

申请号：US11150191

申请日：2005-06-13

申请人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su

发明人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su

IPC分类号： H02J7/00

CPC分类号： H02J7/0052

摘要： In a battery charger using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for generating a charging current to charge a battery, thereby requesting no additional control circuit to control the depletion mode transistor, reducing the circuit size, and lowering the cost.

摘要翻译： 在使用耗尽型晶体管作为电流源的电池充电器中，耗尽型晶体管是自偏压的，用于产生充电电流以对电池充电，从而不需要额外的控制电路来控制耗尽型晶体管，从而减少电路 尺寸，降低成本。

公开(公告)号：US07838901B2

公开(公告)日：2010-11-23

申请号：US12385719

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US07795855B2

公开(公告)日：2010-09-14

申请号：US11826449

申请日：2007-07-16

申请人： Hung-Der Su ,  Jing-Meng Liu

发明人： Hung-Der Su ,  Jing-Meng Liu

IPC分类号： G05F1/40

CPC分类号： H02M1/08 ,  H02M3/156 ,  Y10T307/858

摘要： Two step driving technique is used to turn on the power switch of a power management apparatus in such a manner that the power switch is weakly turned on first and then goes into a low ON-resistance region. The power switch is so avoided to operate at highest gate and drain voltages simultaneously even a non-uniform turn on happens, and is thereby away from avalanche breakdown. The safe operation region of the power management apparatus is therefore extended with minimum efficiency degradation.

摘要翻译： 使用两步驱动技术，以使得电源开关首先弱开然后进入低导通电阻区域的方式来接通电源管理装置的电源开关。 电源开关如此避免同时在最高的栅极和漏极电压下工作，即使发生不均匀的导通，也因此远离雪崩击穿。 因此，功率管理装置的安全操作区域以最小的效率降低而延长。

公开(公告)号：US20090206921A1

公开(公告)日：2009-08-20

申请号：US12385717

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： G05F3/02

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US07436640B2

公开(公告)日：2008-10-14

申请号：US11154175

申请日：2005-06-15

申请人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

发明人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

IPC分类号： H02H9/00

CPC分类号： H02M3/155 ,  H02M1/32 ,  H03K17/08142 ,  H03K17/0822

摘要： A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

摘要翻译： 升压电力管理集成电路芯片包括第一和第二输出焊盘，耦合在第一和第二输出焊盘之间并具有栅极的晶体管开关，以及耦合在第一和第二输出焊盘之间的触发电路，并进一步耦合到 晶体管开关 当在第一和第二输出焊盘之间存在大于触发电压电平的瞬时电压时，触发电路驱动晶体管开关导通，以使电流流过晶体管开关。

公开(公告)号：US20070147099A1

公开(公告)日：2007-06-28

申请号：US11708325

申请日：2007-02-21

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H02M7/537

CPC分类号： H02M3/158 ,  H02M3/155 ,  H03K17/063 ,  H03K17/6871 ,  H03K17/693 ,  H03K2017/6875

摘要： Electronic circuits use low-cost depletion-mode JFET to serve as power switch. Since depletion-mode JFET has smaller conductive resistance and is majority carrier device, the energy loss is less when current flows through the depletion-mode JFET, and faster switching speed is obtained, thereby enhancing the efficiency of the electronic circuits.

公开(公告)号：US20070126057A1

公开(公告)日：2007-06-07

申请号：US11605438

申请日：2006-11-29

申请人： Jing-Meng Liu ,  Hung-Der Su

发明人： Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0878

摘要： In a lateral DMOS device which has a drain diffusion region, an insulator is provided on the drain diffusion region. The insulator is helpful to reduce the lateral electric field under silicon surface. The gate of the DMOS does not overlap with the insulator over the drain diffusion region such that the lateral DMOS device is insensitive to oxide corner loss.

摘要翻译： 在具有漏极扩散区域的横向DMOS器件中，在漏极扩散区域上设置绝缘体。 绝缘子有助于减小硅表面下的横向电场。 DMOS的栅极不与漏极扩散区域上的绝缘体重叠，使得侧向DMOS器件对氧化物角损失不敏感。

公开(公告)号：US20060126237A1

公开(公告)日：2006-06-15

申请号：US11154175

申请日：2005-06-15

申请人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

发明人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

IPC分类号： H02H9/00

CPC分类号： H02M3/155 ,  H02M1/32 ,  H03K17/08142 ,  H03K17/0822

摘要： A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

摘要翻译： 升压电力管理集成电路芯片包括第一和第二输出焊盘，耦合在第一和第二输出焊盘之间并具有栅极的晶体管开关，以及耦合在第一和第二输出焊盘之间的触发电路，并进一步耦合到 晶体管开关 当在第一和第二输出焊盘之间存在大于触发电压电平的瞬时电压时，触发电路驱动晶体管开关导通，以使电流流过晶体管开关。

公开(公告)号：US20090237062A1

公开(公告)日：2009-09-24

申请号：US12385721

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： G05F3/24

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US20090206922A1

公开(公告)日：2009-08-20

申请号：US12385718

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： G05F3/02

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.