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    Method for end point detection of polysilicon chemical mechanical polishing in an anti-fuse memory device
    1.
    发明申请
    Method for end point detection of polysilicon chemical mechanical polishing in an anti-fuse memory device 有权
    反熔丝存储器件中多晶硅化学机械抛光的端点检测方法

    公开(公告)号：US20050170563A1

    公开(公告)日：2005-08-04

    申请号：US10767276

    申请日：2004-01-29

    申请人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L21/461 ,  H01L21/768 ,  H01L21/82 ,  H01L27/10

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    摘要翻译： 实现了在制造集成电路器件时抛光导线的新方法。 该方法包括提供覆盖在衬底上的多条导线。 将高密度等离子体（HDP）氧化物层沉积在衬底和导电线上。 在导电线之间的区域中，HDP氧化物层的第一平坦表面形成在导线的顶部下方。 将HDP氧化物层溅射到覆盖导电线上，使得HDP氧化物层的第二平面形成在导电线之上。 抛光停止层沉积在HDP氧化物层上。 沉积在抛光停止层上的膜层。 将薄膜层抛光到覆盖第二平面顶表面的抛光停止层。 将薄膜层，抛光阻止层和导电线抛光到覆盖第一平面顶表面的抛光停止层，以完成导线的抛光。

    Booster power management integrated circuit chip with ESD protection between output pads thereof
    3.
    发明授权
    Booster power management integrated circuit chip with ESD protection between output pads thereof 失效
    增压器电源管理集成电路芯片，其输出焊盘之间具有ESD保护

    公开(公告)号：US07436640B2

    公开(公告)日：2008-10-14

    申请号：US11154175

    申请日：2005-06-15

    申请人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

    发明人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

    IPC分类号： H02H9/00

    CPC分类号： H02M3/155 ,  H02M1/32 ,  H03K17/08142 ,  H03K17/0822

    摘要： A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

    摘要翻译： 升压电力管理集成电路芯片包括第一和第二输出焊盘，耦合在第一和第二输出焊盘之间并具有栅极的晶体管开关，以及耦合在第一和第二输出焊盘之间的触发电路，并进一步耦合到 晶体管开关 当在第一和第二输出焊盘之间存在大于触发电压电平的瞬时电压时，触发电路驱动晶体管开关导通，以使电流流过晶体管开关。

    Booster power management integrated circuit chip with ESD protection between output pads thereof
    4.
    发明申请
    Booster power management integrated circuit chip with ESD protection between output pads thereof 失效
    增压器电源管理集成电路芯片，其输出焊盘之间具有ESD保护

    公开(公告)号：US20060126237A1

    公开(公告)日：2006-06-15

    申请号：US11154175

    申请日：2005-06-15

    申请人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

    发明人： Hung-Der Su ,  Jing-Meng Liu ,  Chiang-Yung Ku

    IPC分类号： H02H9/00

    CPC分类号： H02M3/155 ,  H02M1/32 ,  H03K17/08142 ,  H03K17/0822

    摘要： A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

    摘要翻译： 升压电力管理集成电路芯片包括第一和第二输出焊盘，耦合在第一和第二输出焊盘之间并具有栅极的晶体管开关，以及耦合在第一和第二输出焊盘之间的触发电路，并进一步耦合到 晶体管开关 当在第一和第二输出焊盘之间存在大于触发电压电平的瞬时电压时，触发电路驱动晶体管开关导通，以使电流流过晶体管开关。

    Nonvolatile semiconductor memory device
    5.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07608926B2

    公开(公告)日：2009-10-27

    申请号：US11326904

    申请日：2006-01-06

    申请人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    摘要翻译： 实现了在制造集成电路器件时抛光导线的新方法。 该方法包括提供覆盖在衬底上的多条导线。 将高密度等离子体（HDP）氧化物层沉积在衬底和导电线上。 在导电线之间的区域中，HDP氧化物层的第一平坦表面形成在导线的顶部下方。 将HDP氧化物层溅射到覆盖导电线上，使得HDP氧化物层的第二平面形成在导电线之上。 抛光停止层沉积在HDP氧化物层上。 沉积在抛光停止层上的膜层。 将薄膜层抛光至覆盖第二平面顶表面的抛光停止层。 将薄膜层，抛光阻止层和导电线抛光到覆盖第一平面顶表面的抛光停止层，以完成导线的抛光。

    Nonvolatile semiconductor memory device
    6.
    发明申请
    Nonvolatile semiconductor memory device 有权

    公开(公告)号：US20060186546A1

    公开(公告)日：2006-08-24

    申请号：US11326904

    申请日：2006-01-06

    申请人： Kern Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L23/52

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device
    7.
    发明授权
    Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device 有权
    用于端点检测的方法多晶硅化学机械抛光在反熔丝存储器件中

    公开(公告)号：US07012021B2

    公开(公告)日：2006-03-14

    申请号：US10767276

    申请日：2004-01-29

    申请人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    摘要翻译： 实现了在制造集成电路器件时抛光导线的新方法。 该方法包括提供覆盖在衬底上的多条导线。 将高密度等离子体（HDP）氧化物层沉积在衬底和导电线上。 在导电线之间的区域中，HDP氧化物层的第一平坦表面形成在导线的顶部下方。 将HDP氧化物层溅射到覆盖导电线上，使得HDP氧化物层的第二平面形成在导电线之上。 抛光停止层沉积在HDP氧化物层上。 沉积在抛光停止层上的膜层。 将薄膜层抛光至覆盖第二平面顶表面的抛光停止层。 将薄膜层，抛光阻止层和导电线抛光到覆盖第一平面顶表面的抛光停止层，以完成导线的抛光。