OFFSET CORRECTION FOR SENSE AMPLIFIER
    22.
    发明申请
    OFFSET CORRECTION FOR SENSE AMPLIFIER 有权
    用于感应放大器的偏移校正

    公开(公告)号:US20170019119A1

    公开(公告)日:2017-01-19

    申请号:US15277076

    申请日:2016-09-27

    CPC classification number: H03M1/1023 H03M1/66 H04L25/03057 H04L25/03878

    Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地,本发明的实施例提供了一种用于SERDES系统的偏移校正技术。 用于接收输入数据信号的CTLE模块被设置为隔离模式,并且一个或多个感测放大器在隔离模式期间异步地进行数据采样。 在隔离模式下,不直接连接到读出放大器的CLTE被关闭。 在隔离模式下采样的数据用于确定稍后在SERDES系统的正常操作中使用的偏移值。 还有其它实施例。

    CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER
    23.
    发明申请
    CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER 有权
    具有变压器的电流模式逻辑的连续时间线性均衡

    公开(公告)号:US20160294582A1

    公开(公告)日:2016-10-06

    申请号:US15074530

    申请日:2016-03-18

    CPC classification number: H04L25/03057 H03K19/094 H04L25/0272 H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说,本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器,CML的输出相等。 还有其它实施例。

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