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    CHARGE PUMP CIRCUITS FOR CLOCK AND DATA RECOVERY
    3.
    发明申请
    CHARGE PUMP CIRCUITS FOR CLOCK AND DATA RECOVERY 审中-公开

    公开(公告)号：US20200059348A1

    公开(公告)日：2020-02-20

    申请号：US16664666

    申请日：2019-10-25

    Applicant: INPHI CORPORATION

    Inventor： Simon FOREY ,  Parmanand MISHRA ,  Michael S. HARWOOD ,  Rajasekhar NAGULAPALLI

    IPC: H04L7/00 ,  H03L7/093 ,  H04L7/033 ,  H03L7/08 ,  H02M3/07

    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

    LOSS OF SIGNAL DETECTION ON CDR
    4.
    发明申请
    LOSS OF SIGNAL DETECTION ON CDR 审中-公开
    信号丢失在CDR上的检测

    公开(公告)号：US20170063520A1

    公开(公告)日：2017-03-02

    申请号：US15337072

    申请日：2016-10-28

    Applicant: INPHI CORPORATION

    Inventor： Parmanand MISHRA ,  Simon FOREY

    IPC: H04L7/033 ,  H04L27/01 ,  H04B17/318 ,  H04L12/26

    CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03M9/00 ,  H04B17/318 ,  H04L7/0083 ,  H04L7/0091 ,  H04L7/033 ,  H04L25/0262 ,  H04L27/01 ,  H04L43/04 ,  H04L43/16

    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供了一种用于检测信号损失的技术。 对输入数据流进行采样，并相应地生成恢复的时钟信号。 通过传输PLL产生比恢复的时钟信号高的频率的输出时钟信号。 将恢复的时钟信号的频率与输出时钟信号的分频进行比较。 如果恢复的时钟信号和输出时钟信号之间的差异大于阈值，则提供信号指示的丢失。 还有其它实施例。

    FREQUENCY ACQUISITION FOR SERDES RECEIVERS
    5.
    发明申请
    FREQUENCY ACQUISITION FOR SERDES RECEIVERS 有权
    频率接收服务器接收器

    公开(公告)号：US20160330015A1

    公开(公告)日：2016-11-10

    申请号：US15214212

    申请日：2016-07-19

    Applicant: INPHI CORPORATION

    Inventor： Simon FOREY ,  Parmanand MISHRA ,  Sean BATTY

    IPC: H04L7/00 ,  H04L27/152

    CPC classification number: H04L7/0087 ,  H03M9/00 ,  H04B10/6164 ,  H04L7/0004 ,  H04L7/0331 ,  H04L7/06 ,  H04L27/152

    Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供一种通过扫过预定频率范围来获取采样频率的方法，在预定频率范围内以不同频率执行数据采样，并且基于最大早峰频率来确定用于采样数据的目标频率 和最大晚峰频率。 还有其它实施例。

    SERDES WITH HIGH-BANDWITH LOW-LATENCY CLOCK AND DATA RECOVERY
    10.
    发明申请
    SERDES WITH HIGH-BANDWITH LOW-LATENCY CLOCK AND DATA RECOVERY 有权
    具有高带宽低延迟时钟和数据恢复的SERDES

    公开(公告)号：US20170078084A1

    公开(公告)日：2017-03-16

    申请号：US15162402

    申请日：2016-05-23

    Applicant: INPHI CORPORATION

    Inventor： Simon FOREY ,  Parmanand MISHRA

    IPC: H04L7/033

    CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03M9/00 ,  H04L7/033

    Abstract: The present application is directed to data communication. More specifically, embodiments of the present invention provide a SerDes system that includes multiple communication lanes that are aligned using a clock signal. Each of the communication lanes comprises a receiver, a buffer, and a transmitter. The receiver uses multiple sampling lanes for data sampling and clock recovery. Sampled data are stored at the buffer and transmitted by the transmitter. There are other embodiments as well.

    Abstract translation: 本申请涉及数据通信。 更具体地，本发明的实施例提供了一种SerDes系统，其包括使用时钟信号对准的多个通信通道。 每个通信通道包括接收器，缓冲器和发射器。 接收机使用多个采样通道进行数据采样和时钟恢复。 采样数据存储在缓冲区并由发送器发送。 还有其它实施例。

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