公开(公告)号：US20210110043A1

公开(公告)日：2021-04-15

申请号：US17132188

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Berger ,  Anoop Mukker ,  Karunakara Kotary ,  Nivedita Aggarwal ,  Udy Hershkovitz ,  Arijit Chattopadhyay ,  Jabeena B. Gaibusab ,  Christopher J. Lake

IPC: G06F21/57 ,  G06F21/55 ,  G06F21/79 ,  G06F21/31 ,  G06F12/1081

Abstract: An apparatus to facilitate a computer system platform boot is disclosed. The apparatus comprises a system on chip (SOC), including a cache memory, a storage device to store platform firmware including boot code, a security controller to load the boot code into the cache during a platform reset and a processor to execute the boot code from the cache memory to initiate the SOC.

公开(公告)号：US20190391949A1

公开(公告)日：2019-12-26

申请号：US16254266

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/42 ,  G06F1/08 ,  G06F1/24 ,  G06F1/3287 ,  G06F9/4401

Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

公开(公告)号：US09904650B2

公开(公告)日：2018-02-27

申请号：US14678712

申请日：2015-04-03

Applicant: Intel Corporation

Inventor： Karthi R. Vadivelu ,  Sridharan Ranganathan ,  Anoop Mukker ,  Satheesh Chellappan

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/12

CPC classification number: G06F13/426 ,  G06F13/122 ,  G06F13/126 ,  G06F13/387 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.